Nonvolatile memory cell comprising a reduced height vertical diode

1. A method for forming a plurality of nonvolatile memory cells, the method comprising:

forming a plurality of substantially parallel, substantially coplanar first conductors at a first height above a substrate;

forming a plurality of vertically oriented first pillars comprising vertically oriented first polysilicon diodes above the first conductors; and

forming a plurality of substantially parallel, substantially coplanar second conductors above the first pillars,

wherein, after formation of the second conductors, the first polysilicon diodes have a height between about 500 angstroms and about 3500 angstroms.

2. The method of claim 1 wherein the first polysilicon diodes have a height between about 800 angstroms and about 2500 angstroms.

3. The method of claim 1 wherein the step of forming the first conductors comprises:

depositing a first conductive layer;

patterning and etching the first conductive layer into the first conductors;

depositing a first dielectric material on and between the first conductors; and

planarizing to expose the first conductors separated by the first dielectric material.

4. The method of claim 3 wherein the step of forming the first pillars comprises:

depositing a semiconductor layer stack on the first conductors and the first dielectric material; and

patterning and etching the semiconductor layer stack to form the first pillars.

5. The method of claim 4 wherein the step of forming the first pillars further comprises forming a top heavily doped region in each of the first pillars by ion implantation.

6. The method of claim 5 wherein, during ion implantation, BF 2 ions are implanted.

7. The method of claim 5 wherein the ion implantation is performed at an implant energy of more than about 4 keV.

8. The method of claim 4 wherein the step of forming the semiconductor layerstack comprises depositing a thickness of between about 1200 angstroms and about 4300 angstroms of semiconductor material.

9. The method of claim 8 wherein the thickness of the semiconductor material is between about 1600 angstroms and about 4000 angstroms.

10. The method of claim 8 further comprising, after the step of patterning and etching the semiconductor layer stack:

depositing a second dielectric material over and between the first pillars; and

planarizing to expose tops of the first pillars.

11. The method of claim 10 further comprising, after the step of planarizing to expose the tops of the first pillars, forming an oxide layer by oxidation of a portion of the first pillars.

12. The method of claim 10 wherein the planarizing step comprises chemical mechanical planarization.

13. The method of claim 4 wherein the step of forming the first pillars further comprises forming a top heavily doped region and a bottom heavily doped region in each of the first diodes, wherein the top and the bottom heavily doped regions are not doped by in situ doping.

14. The method of claim 13 wherein the top heavily doped region or the bottom heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

15. The method of claim 14 wherein the top heavily doped region or the bottom heavily doped region is doped by ion implantation.

16. The method of claim 15 wherein, during ion implantation, arsenic ions are implanted.

17. The method of claim 15 wherein, during ion implantation, BF 2 ions are implanted.

18. The method of claim 4 wherein the step of forming the first pillars further comprises forming a bottom heavily doped region in each of the first diodes by in situ doping.

19. A method for forming a nonvolatile memory cell, the method comprising:

forming a rail-shaped first conductor;

forming a vertically oriented junction diode comprising polysilicon above the first conductor; and

forming a rail-shaped second conductor above the junction diode,

wherein, after formation of the second conductor, the height of the junction diode is between about 500 angstroms and about 3500 angstroms.

20. The method of claim 19 wherein each of the first conductor, the junction diode, and the second conductor is formed in a separate patterning and etching step.

21. The method of claim 19 wherein the height of the junction diode is between about 800 angstroms and about 3000 angstroms.

22. The method of claim 21 wherein, after formation of the second conductor, the height of the junction diode is between about 1300 angstroms and about 2500 angstroms.

23. The method of claim 19 wherein the step of forming the junction diode comprises:

depositing a semiconductor layer stack; and

patterning and etching the semiconductor layer stack into first pillars.

24. The method of claim 23 wherein each junction diode comprises:

a bottom heavily doped region of a first conductivity type;

a middle lightly doped or intrinsic region; and

a top heavily doped region of a second conductivity type, the second conductivity type opposite the first conductivity type.

25. The method of claim 24 wherein the top heavily doped region is not doped by in situ doping.

26. The method of claim 25 wherein the top heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

27. The method of claim 26 wherein the top heavily doped region is doped by ion implantation.

28. The method of claim 27 wherein the top heavily doped region is doped with BF 2 ions.

29. The method of claim 27 wherein the ion implantation is performed with an implant energy greater than about 4 kiloelectron volts.

30. The method of claim 24 wherein the bottom heavily doped region is not doped by in situ doping.

31. The method of claim 30 wherein the bottom heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

32. The method of claim 31 wherein the bottom heavily doped region is doped by ion implantation.

33. The method of claim 32 wherein the top heavily doped region is doped with arsenic ions.