Three dimensional six surface conformal die coating
View Patent ↗Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.
1. Individual freestanding silicon die, including six surfaces, which have been singulated from a semiconductor wafer, the die being coated on all six surfaces with a parylene film which has been applied to all surfaces; the parylene film providing electrical insulation and serving as a mechanical protection for the surfaces to prevent chipping and cracking of the silicon die.
2. The die as in claim 1 including openings in the parylene film where the parylene film has been removed to expose a specific layer or feature underneath the insulating material.
3. The die as in claim 2 wherein the opening is above electrical connection pads above circuitry on a top surface of the die.
4. The die as in claim 2 wherein the opening is above optical emitters or sensors on a top surface of the die.
5. The die as in claim 2 wherein the openings are formed through the use of a laser to remove, or ablate, the polymer material from above a specific layer or feature.