Patent Assignment
Reel/Frame 029683/0797
Assignment of Assignor's Interest
Recorded: 2013-01-23
Pages: 10
Assignor
VERTICAL CIRCUITS, INC.
Executed: 2012-11-14
Assignee
VERTICAL CIRCUITS SOLUTIONS, INC.
10 VICTOR SQUARE, SCOTTS VALLEY, CALIFORNIA, USA 95066
Covered Properties
(45)
Extended Cavity Laser Readout Apparatus
Patent:
4,658,146 →
Application:
06/709,267 →
Extended Cavity Laser Recording Method and Apparatus
Patent:
4,707,814 →
Application:
06/711,842 →
Semiconductor Wafer Array
Patent:
4,897,708 →
Application:
06/887,129 →
Semiconductor Wafer Array with Electrically Conductive Compliant Material
Patent:
4,954,875 →
Application:
07/114,633 →
Vertical Interconnect Process for Silicon Segments
Patent:
5,675,180 →
Application:
08/265,081 →
A Conductive Expoxy Flip-Chip Package and Method
Patent:
5,657,206 →
Application:
08/374,421 →
Silicon Segment Programming Method and Apparatus
Patent:
5,698,895 →
Application:
08/376,149 →
Vertical Interconnect Process for Silicon Segments
Patent:
5,661,087 →
Application:
08/476,623 →
Conductive Epoxy Flip-Chip Package and Method
Patent:
6,134,118 →
Application:
08/834,798 →
Vertical Interconnect Process for Silicon Segments
Patent:
6,188,126 →
Application:
08/842,448 →
Silicon Segment Programming Method
Patent:
5,994,170 →
Application:
08/845,654 →
Speaker Diaphragm
Patent:
5,936,302 →
Application:
08/845,655 →
Vertical Interconnect Process for Silicon Segments
Patent:
5,837,566 →
Application:
08/847,309 →
Conductive Epoxy Flip-Chip on Chip
Application:
08/902,169 →
Vertical Interconnect Process for Silicon Segments with Dielectric Isolation
Patent:
6,255,726 →
Application:
08/915,620 →
Method for Forming Conductive Epoxy Flip-Chip on Chip
Patent:
6,098,278 →
Application:
08/917,447 →
Conductive Epoxy Flip-Chip on Chip
Patent:
6,271,598 →
Application:
08/918,500 →
Vertical Interconnect Process for Silicon Segments with Thermally Conductive Epoxy Preform
Patent:
6,124,633 →
Application:
08/918,501 →
Method for Forming Vertical Interconnect Process for Silicon Segments with Thermally Conductive Epoxy Preform
Patent:
5,891,761 →
Application:
08/918,502 →
Method for Forming Vertical Interconnect Process for Silicon Segments with Dielectric Isolation
Patent:
6,080,596 →
Application:
08/920,273 →
Method for Forming Vertical Interconnect Process for Silicon Segments with Thermally Conductive Epoxy Preform
Patent:
6,177,296 →
Application:
09/273,941 →
Silicon Segment Programming Apparatus and Three Terminal Fuse Configuration
Patent:
6,486,528 →
Application:
09/378,879 →
Vertically integrated chip on chip circuit stack
Application:
09/620,011 →
Three Dimensional Six Surface Conformal Die Coating
Stacked Die Bga or Lga Component Assembly
Micropede Stacked Die Component Assembly
Assembly Having Stacked Die Mounted on Substrate
Die Assembly Having Electrical Interconnect
Three Dimensional Six Surface Conformal Die Coating
Application:
11/849,162 →
Publication:
US 2007/0290377
Vertical Electrical Interconnect Formed on Support Prior to Die Mount
Electrically Interconnected Stacked Die Assemblies
Wafer Level Surface Passivation of Stackable Integrated Circuit Chips
Three-Dimensional Circuitry Formed on Integrated Circuit Device Using Two-Dimensional Fabrication
Application:
12/143,157 →
Publication:
US 2008/0315407
Electrically Interconnected Stacked Die Assemblies
Wafer Level Surface Passivation of Stackable Integrated Circuit Chips
Three dimensional six surface conformal die coating
Application:
60/561,847 →
High density low parasitic stacked die micropede component
Application:
60/561,848 →
High density low parasitic stacked die BGA or LGA component assembly
Application:
60/561,849 →
Vertical Electrical Interconnect Formed On Substrate Prior to Die Mount
Application:
60/895,305 →
Semiconductor Die Coating and Interconnection Fixture and Method
Application:
60/943,211 →
Coinstack Method for Optimized Integrated Circuit Chip Interconnection
Application:
60/943,252 →
Wafer Level Surface Passivation of Stackable Integrated Circuit Chips
Application:
60/945,005 →
Three-Dimensional Circuitry Formed On Integrated Circuit Device Using Two-Dimensional Fabrication
Application:
60/945,274 →
Surface Passivation of Stackable Integrated Circuit Chips at Wafer Level
Application:
60/956,348 →
Stacked die vertical interconnect formed by transfer of interconnect material
Application:
60/965,184 →
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 24, 2012
From: VERTICAL CIRCUITS, INC.
To: VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 029186/0755 →
Assignment of Assignor's Interest
Jan 10, 2013
From: PEDERSEN, DAVID V.; FINLEY, MICHAEL G.; SAUTTER, KENNETH M.
To: CUBIC MEMORY, INC.
Reel/Frame 029626/0970 →
Assignment of Assignor's Interest
Jan 10, 2013
From: PEDERSEN, DAVID V.; FINLEY, MICHAEL G.; SAUTTER, KENNETH M.
To: CUBIC MEMORY, INC.
Reel/Frame 029626/0991 →
Assignment of Assignor's Interest
Jan 10, 2013
From: PEDERSEN, DAVID V.; FINLEY, MICHAEL G.; SAUTTER, KENNETH M.
To: CUBIC MEMORY, INC.
Reel/Frame 029627/0001 →
Assignment of Assignor's Interest
Jan 15, 2013
From: PEDERSEN, DAVID V.; FINLEY, MICHAEL G.; SAUTTER, KENNETH M.
To: CUBIC MEMORY, INC.
Reel/Frame 029645/0465 →
Assignment of Assignor's Interest
Jan 16, 2013
From: PEDERSEN, DAVID V.; FINLEY, MICHAEL G.; SAUTTER, KENNETH M.
To: CUBIC MEMORY, INC.
Reel/Frame 029646/0558 →
Change of Name
Jan 22, 2013
From: CUBIC MEMORY, INC.
To: VERTICAL CIRCUITS, INC.
Reel/Frame 029674/0462 →
Change of Name
Jan 24, 2013
From: VERTICAL CIRCUITS SOLUTIONS, INC.
To: VERTICAL CIRCUITS, INC.
Reel/Frame 029686/0255 →
Assignment of Assignor's Interest
Jan 30, 2013
From: VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: INVENSAS CORPORATION
Reel/Frame 029736/0944 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →