Off-chip data relocation
View Patent ↗The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.
1. A memory system, comprising:
a plurality of memory chips, each including:
a memory array; and
a read/write buffer associated with the memory array;
a controller for managing data stored in the memory system and controlling the transfer of data within the memory system; and
a bus connectable to the controller and the memory arrays for the transfer of data within the memory system,
wherein the controller can select any of said arrays as a source array and any of the other of said arrays as a destination array for a transfer of a page of data between the respective buffers of said source and destination arrays along said bus a subunit of said page at a time, and
wherein the controller can modify selected subunits in the controller as part of said transfer without temporarily storing the non-selected subunits in the controller as part of said transfer.
2. The memory system of claim 1 , wherein said transfer is performed using an EDO-type timing.
3. The memory system of claim 1 , wherein concurrently with transferring a page of data between the respective buffers of said source and destination arrays, the controller can copy said page of data to the controller and therein perform an error detection and correction operation on the copy of said page.
4. The memory system of claim 3 , wherein subsequently to performing an error detection and correction operation on the copy of said page, the controller can transfer a corrected copy of said page to the respective buffer of said destination array.
5. The memory system of claim 1 , wherein the controller can transfer said page of data to the buffer of said destination array when the destination array is busy with a programming operation.
6. A method of operating a memory system, the memory system comprising a plurality of memory chips, each of which includes a memory array and a read/write buffer associated with the memory array, a controller for managing data stored in the memory system and controlling the transfer of data within the memory system, and a bus connectable to the controller and the memory arrays for the transfer of data within the memory system, the method comprising:
selecting the array of a first of the memory chips as a source by the controller;
selecting the array of a second of the memory chips as a destination by the controller, wherein the first and second memory chips can be any of said plurality of memory chips;
transferring a page of data between the respective buffers of said source and destination arrays along said bus a subunit of said page at a time;
selecting by the controller of one or more of the subunits by the controller; and
modifying the selected subunits in the controller as part of said transfer without temporarily storing the non-selected subunits in the controller as part of said transfer.
7. The method of claim 6 , wherein said transfer is performed using an EDO-type timing.
8. The method of claim 6 , further comprising:
concurrently with transferring the page of data between the respective buffers of said source and destination arrays, copying said page of data to the controller and performing therein an error detection and correction operation on the copy of said page.
9. The method of claim 8 , further comprising:
subsequently to performing an error detection and correction operation on the copy of said page, transferring a corrected copy of said page to the respective buffer of said destination array.
10. The method system of claim 6 , wherein the controller transfers said page of data to the buffer of said destination array when the destination array is busy with a programming operation.