Memory control circuit and microprocessory system for pre-fetching instructions
View Patent ↗A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU executes a branch instruction thereafter, if the branch-destination-instruction address output from the CPU matches an instruction address in the branch-destination buffer, the corresponding branch-destination instruction stored in the branch-destination buffer is sent to the CPU. When a branch instruction is executed, an address comparison circuit compares the branch-destination-instruction address with the branch-source-instruction address. A buffer-update control circuit updates data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the instruction address has been changed in the negative direction by the instruction branch.
1. A memory control circuit provided with an instruction pre-fetch function, for controlling the reading of instructions to be fetched by a CPU (Central Processing Unit), from a memory, comprising:
a branch-destination buffer for caching a branch-destination instruction and a branch-destination-instruction address when an instruction address output from the CPU becomes inconsecutive to one another due to a branch instruction, and for outputting, when the instruction address output from the CPU matches a cached instruction address, the corresponding branch-destination instruction to the CPU;
an address comparison circuit for comparing the branch-destination-instruction address determined by the branch instruction with a branch-source-instruction address;
a difference comparison circuit for comparing the difference between a plurality of bits of the branch-source-instruction address and a plurality of bits of the branch-destination-instruction address determined by the branch instruction with a predetermined reference value; and
a buffer-update control circuit for updating data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the branch-destination-instruction address is in a negative direction from the branch-source-instruction address and the difference comparison circuit determines that the difference is equal to or smaller than the reference value;
wherein, when the address comparison circuit receives a branch signal reporting that the instruction address output from the CPU has become inconsecutive to one another, from the CPU, the address comparison circuit compares the branch-destination-instruction address determined by the branch instruction with the branch-source-instruction address.
2. The memory control circuit according to claim 1 , further comprising an address hold circuit, when the renewed instruction address is output from the CPU, the address hold circuit holding the immediately preceding instruction address is output from the CPU;
wherein, when the address comparison circuit receives the branch signal, the address comparison circuit compares the branch-destination-instruction address output from the CPU with the instruction address held by the address hold circuit.
3. A microprocessor system provided with a function for pre-fetching an instruction to be sent to a CPU, from a memory, comprising:
a branch-signal output circuit for outputting a branch signal reporting that the CPU has executed a branch instruction which makes an instruction address inconsecutive to one another;
a branch-destination buffer for caching a branch-destination instruction and a branch-destination-instruction address determined by the branch instruction, and for outputting, when the instruction address output from the CPU matches a cached instruction address, the corresponding branch-destination instruction to the CPU;
an address comparison circuit for comparing the branch-destination-instruction address determined by the branch instruction which has been executed, with a branch-source-instruction address when the address comparison circuit receives the branch signal;
a difference comparison circuit for comparing the difference between a plurality of bits of the branch-source-instruction address and a plurality of bits of the branch-destination-instruction address determined by the branch instruction with a predetermined reference value; and
a buffer-update control circuit for updating data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the branch-destination-instruction address is in a negative direction from the branch-source-instruction address and the difference comparison circuit determines that the difference is equal to or smaller than the reference value.
4. A microprocessor system provided with a function for pre-fetching an instruction to be sent to a CPU, comprising:
a buffer-update control circuit to load a branch-destination-instructions following a branch-source-instruction, in a branch-destination buffer, only when a branch-destination-instruction address is in a negative direction from a branch-source-instruction address, and a difference not indicating a subroutine branch between a plurality of bits of the branch-source-instruction address and a plurality of bits of the branch-destination-instruction address is equal to or smaller than a reference value.
5. A method, comprising:
comparing, by a processor, a branch destination address provided by a branch instruction with a branch source address and caching a branch destination instruction in a buffer when the branch source address and branch destination address are inconsecutive;
comparing, by the processor, a distance between the branch source address and the branch destination address with a reference value by comparing a difference between a plurality of bits of the branch source address and a plurality of bits of the branch destination address; and
loading, by the processor, the cached branch destination instruction from the buffer when the distance of the branch destination address to the branch source address is negative and less than or equal to the reference value.