Methods of forming wells in semiconductor devices
View Patent ↗Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed method includes forming a trench in a surface of a substrate to define a field area, forming a first conductive type well in a first active area of the substrate, forming a second conductive type well in a second active area of the substrate, and filling up the trench with a dielectric.
1. A method of forming a well in a semiconductor substrate comprising:
forming an STI trench in a surface of a substrate to define a field area;
forming a first ion implantation mask over the substrate and the trench such that a first active area and a first part of the trench are exposed;
forming a first conductive type well in the first active area of the substrate and under the first part of the trench so that an end point of the first conductive type well under the first part of the trench is deeper than a bottom of the first conductive type well in the first active area;
forming a second ion implantation mask over the first active area and the first part of the trench;
forming a second conductive type well in a second active area of the substrate and under a second part of the trench so that an end point of the second conductive type well under the second part of the trench is deeper than a bottom of the second conductive type well in the second active area, wherein the first and second conductive type wells meet under the trench and the end points of the first and second conductive type wells where the first and second conductive type wells meet are deeper than bottoms of the first and second conductive type wells in the first and second active areas; and
filling the trench with a dielectric after forming the first and second conductive type wells.
2. A method as defined by claim 1 , wherein the first and second active areas are isolated from each other by the field area.
3. A method as defined by claim 1 , wherein forming the first conductive type well comprises:
implanting a first conductive type dopant into the substrate exposed by the first ion implantation mask; and
removing the first ion implantation mask.
4. A method as defined by claim 3 , wherein the first ion implantation mask comprises a first photoresist pattern.
5. A method as defined by claim 1 , wherein forming the second conductive type well comprises:
implanting a second conductive type dopant into the substrate exposed by the second ion implantation mask; and
removing the second ion implantation mask.
6. A method as defined by claim 5 , wherein the second ion implantation mask comprises a first photoresist pattern.
7. A method as defined by claim 1 , wherein the semiconductor substrate comprises a silicon substrate having a thermal oxide layer thereon.
8. A method as defined by claim 7 , wherein the semiconductor substrate further comprises a silicon nitride layer on the thermal oxide layer.
9. A method as defined by claim 1 , wherein the semiconductor substrate comprises a silicon substrate having a silicon nitride layer over the first and second active areas.
10. A method as defined by claim 8 , wherein the semiconductor substrate further comprises a TEOS layer on the silicon nitride layer.
11. A method as defined by claim 1 , wherein the semiconductor substrate comprises a silicon substrate having a TEOS layer over the first and second active areas.
12. A method as defined by claim 1 , further comprising forming an oxide layer on an inside surface of the trench.
13. A method as defined by claim 12 , wherein the oxide layer is formed prior to forming the first and second conductive type wells.
14. A method as defined by claim 1 , further comprising planarizing the dielectric by chemical mechanical polishing.
15. A method as defined by claim 8 , further comprising planarizing the dielectric by chemical mechanical polishing.
16. A method as defined by claim 10 , further comprising planarizing the dielectric by chemical mechanical polishing.
17. A method as defined by claim 15 , comprising sufficient chemical mechanical polishing to remove the silicon nitride layer.
18. A method as defined by claim 1 , wherein filling the trench with the dielectric comprises depositing dielectric material on the semiconductor substrate.
19. A method as defined by claim 1 , wherein forming an STI trench comprises:
forming a photoresist pattern to define an area of the trench and exposing a surface of the TEOS layer, and
etching the TEOS layer, the silicon nitride, the oxide layer, and the silicon substrate sequentially to form the STI trench.
20. A method as defined by claim 19 , further comprising STI rounding by additional etching of the trench.