Semiconductor device and fabricating method thereof
View Patent ↗Semiconductor devices and a fabricating method therefore are disclosed. One example method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode.
1. A semiconductor device comprising:
a gate electrode on a trench in a semiconductor substrate;
a second gate oxide layer in the trench between the gate electrode and the semiconductor substrate;
sidewall floating gates on the lower part of the lateral faces of the gate electrode;
a first gate oxide layer formed in the trench between the sidewall floating gates and a portion of the semiconductor substrate along the bottom of the trench;
a second block oxide layer between the gate electrode and the sidewall floating gates;
source and drain regions around a portion of the sidewall floating gates in the trench, wherein the source region is provided at one side of the trench and the drain region is provided along the same horizontal plane at the opposite side of the trench, and wherein the source region is elevated to the same level as the drain region;
a channel formed below a bottom of the trench;
spacers on a portion of the lateral faces of the sidewall floating gates above the trench and on the lateral faces of the gate electrode; and
a first block oxide layer formed on lateral sides of the trench between the sidewall floating gates and the semiconductor substrate and extending along the lateral sides of the sidewall floating gates between the spacers and the sidewall floating gates.
2. A device as defined by claim 1 , further comprising a poly oxide layer between the spacers and the gate electrode.
3. A device as defined by claim 1 , wherein the gate electrode is a T-shaped gate so that an upper part of the gate electrode is wider than a lower part of the gate electrode.
4. A device as defined by claim 1 , wherein the sidewall floating gates are doped with a dopant selected from the group consisting of electrons, holes, negative ions, and positive ions.
5. A device as defined by claim 1 , wherein virtual source and drain extension regions as a strong inversion layer are positioned in the semiconductor substrate under the sidewall floating gates.
6. A device as defined by claim 5 , wherein the virtual source and drain extension regions have a depth between 5 nanometers and 10 nanometers.
7. A device as defined by claim 1 , wherein at least a portion of the gate electrode is in the trench.
8. A device as defined by claim 1 , wherein at least a portion of the sidewall floating gates are in the trench.
9. The device as defined by claim 1 , further comprising a suicide layer on the source and drain regions, wherein a thickness of the suicide layer is thinner than a depth of the source and drain junctions of the source and drain regions.