SRAM devices and methods of fabricating the same

1. An SRAM device, comprising:

first and second load elements, the second load element having a junction layer;

first and second drive transistors, the second drive transistor having a junction layer region;

a common gate electrode connected to a gate electrode of the first load element and a gate electrode of the first drive transistor, the common gate electrode on an isolation layer having an uniform upper surface planar with upper surfaces of the junction layer and the junction layer region and in contact with the junction layer of the second load element and the junction layer region of the second drive transistor;

a silicide layer on the junction layer of the second load element, on the junction layer region of the second drive transistor, and on the common gate electrode; and

an upper line electrically connected to the common gate electrode via only one contact plug in a contact hole that exposes a portion only of the common gate electrode.

2. An SRAM device as defined in claim 1 , wherein the contact hole exposes a portion only of the silicide layer on the common gate electrode.

3. An SRAM device as defined in claim 1 , wherein the isolation layer comprises a shallow trench isolation (STI) layer or a local oxidation of silicon (LOCOS) layer.

4. An SRAM device as defined in claim 1 , wherein the silicide layer is self-aligned (salicide).

5. An SRAM device as defined in claim 4 , wherein the salicide layer comprises a Ti, Cu, Ni or Mo salicide.

6. An SRAM device as defined in claim 1 , wherein the upper line comprises one or more materials selected from Al, Cu or an alloy thereof.

7. An SRAM device as defined in claim 1 , further comprising a borophosphorous silicate glass (BPSG) layer between the silicide layer and the upper line.

8. A method of fabricating an SRAM device having first and second load elements and first and second drive transistors, comprising:

forming a device isolation layer having a uniform upper surface in a semiconductor substrate to define first, second, third and fourth active areas therein;

forming gate electrodes of the second load element and the second drive transistor on the second and fourth active areas;

forming a common gate electrode of the first load element and the first drive transistor on the first and third active areas and on the device isolation area and portions of the second and fourth active areas planar with the upper surface of and adjacent to the device isolation area;

forming source/drain regions on opposite sides of the gate electrodes of the second load element and the second drive transistor;

forming a silicide layer on the source/drain regions and on the common gate electrode prior to forming the insulating layer;

after forming the silicide layer, forming an insulating interlayer on the gate electrodes and the common gate electrode;

forming a contact hole in the insulating interlayer to expose a portion only of the common gate electrode; and

forming a plug in the contact hole.

9. A method as defined in claim 8 , wherein the contact hole exposes at least a portion only of the silicide layer on the common gate electrode.

10. A method as defined in claim 8 , wherein the device isolation layer is formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

11. A method as defined in claim 8 , wherein forming the gate electrodes and the common gate electrode comprises:

growing a gate oxide layer on the active areas by thermal oxidation;

depositing a single conductor layer comprising doped polysilicon on the gate oxide layer; and

selectively patterning the gate oxide layer and the conductor layer.

12. A method as defined in claim 8 , further comprising:

forming spacers on sidewalls of the gate electrodes of the second load element and the second drive transistor prior to forming the source/drain regions; and

forming lightly doped drain (LDD) regions on opposite sides of the gate electrodes of the second load element and the second drive transistor.

13. A method as defined in claim 8 , wherein forming the silicide layer further comprises:

forming a high-melting point metal layer comprising one or more materials selected from Ti, Cu, Ni and Mo on the common gate electrode and the source/drain regions; and

annealing the metal layer by rapid thermal processing (RTP) or furnace annealing.

14. An SRAM device, comprising:

first and second load elements;

first and second drive transistors;

a semiconductor substrate having first, second, third and fourth active areas defined by a device isolation layer having a uniform upper surface planar with upper surfaces of the active areas;

gate electrodes of the second load element and the second drive transistor on the second and fourth active areas;

a common gate electrode on the device isolation layer of the first load element and the first drive transistor in contact with the second and fourth active areas and the device isolation layer;

a silicide layer on the source/drain regions and the common gate electrode;

an insulating interlayer on the gate electrodes and the common gate electrode;

a contact hole in the insulating interlayer to expose a portion only of the common gate electrode; and

a plug in the contact hole.

15. An SRAM device of claim 14 , wherein the contact hole exposes a portion only of the silicide layer on the common gate electrode.

16. An SRAM device as defined in claim 14 , further comprising a shallow trench isolation (STI) layer or a local oxidation of silicon (LOCOS) layer.

17. An SRAM device as defined in claim 14 , wherein the silicide layer is self-aligned (salicide).

18. An SRAM device as defined in claim 17 , wherein the salicide layer comprises a Ti, Cu, Ni or Mo salicide.

19. An SRAM device as defined in claim 14 , wherein the upper line comprises one or more materials selected from Al, Cu or an alloy thereof.

20. An SRAM device as defined in claim 14 , further comprising a borophosphorous silicate glass (BPSG) layer between the silicide layer and the upper line.