Method of fabricating semiconductor device
View Patent ↗A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a semiconductor substrate, forming a channel ion area in the substrate, forming a gate electrode on the gate insulating layer, forming a sidewall insulating layer on the gate electrode, forming lightly doped regions in the substrate adjacent to the channel ion area and aligned with the gate electrode, forming a spacer insulating layer on the sidewall insulating layer, forming spacers on sidewalls of the gate electrode, and forming heavily doped regions in the substrate aligned with the spacer.
1. A method of fabricating a semiconductor device, comprising the steps of:
forming a gate insulating layer on a semiconductor substrate;
after forming said gate insulating layer, forming a channel ion area in the substrate;
after forming said channel ion area, forming a gate electrode on the gate insulating layer;
implanting first ions at a low dose in to substrate using the gate electrode as a mask prior to forming a sidewall insulating layer or a spacer on sidewalls of the gate electrode;
after implanting said first ions, forming the sidewall insulating layer on the gate elcetrode;
implanting second ions at a low dose into the substrate to form lightly doped regions in the substrate adjacent to the channel ion area and aligned with to gate electrode;
forming a spacer insulating layer on the sidewall insulating layer
forming spacers on sidewalls of the gate electrode by etching to spacer insulating layer and the sidewall insulating layer; and
forming heavily doped regions in the substrate aligned wit the spacers.
2. The method of claim 1 , wherein forming the channel ion area comprises implanting impurity ions at a dose of 1E12˜1E14 ions/cm 2 into the substrate.
3. The method of claim 2 , wherein implanting impurity ions comprises implanting BF 2 ions.
4. The method of claim 1 , wherein the sidewall insulating layer comprises an oxide.
5. The method of claim 1 , further comprising forming a device isolation layer by a shallow trench isolation process.
6. The method of claim 1 , wherein forming the gale insulating layer comprises a thermal oxidation process.
7. The method of claim 1 , wherein forming the gate electrode comprises depositing a conductive layer by LPCVD.
8. The method of claim 7 , wherein forming the gate electrode comprises etching the conductive layer and the gate insulating layer until an active area of the semiconductor substrate is exposed.
9. The method of claim 1 , wherein forming the sidewall insulating layer comprises depositing an oxide layer.
10. The method of claim 1 , wherein forming the sidewall insulating layer comprises depositing a TEOS layer.
11. The method of claim 1 , wherein forming the sidewall insulating layer comprises depositing an insulating material to a thickness of 50 ˜200 Å.
12. The method of claim 1 , wherein the substrate comprises a first conductive type single crystalline silicon substrate, and implanting the first ions at a low dose comprises implanting second conductive type ions at a dose of 1E14˜1E15 ions/em 2.
13. The method of claim 1 , wherein the substrate comprises a first conductive type single crystalline silicon substrate, and implanting second ions into the substrate to form lightly doped regions in the substrate comprises implanting second conductive type ions at a dose of 1E14˜1E15 ions/cm 2.
14. The method of claim 1 , wherein forming the spacer insulating layer comprises depositing a nitride layer.
15. The method of claim 1 , wherein forming the spacer insulating layer comprises depositing an insulating material to a thickness of 200˜500 Å.
16. The method of claim 1 , wherein etching the spacer insulating layer and the sidewall insulating layer comprises an etch back process or reactive ion etching.
17. The meted of claim 1 , wherein the substrate comprises a first conductive type single crystalline silicon substrate, and forming heavily doped regions in the substrate comprises implanting second conductive type ions at a dose of 1E15˜1E15 ions/cm 2.
18. The method of claim 1 , further comprising annealing the substrate by rapid thermal processing at a temperature of 800–1000° C. for 10–30 seconds after forming heavily doped regions In the substrate.
19. The method of claim 1 , further comprising forming a silicide layer on the gate electrode and the heavily doped regions.
20. The method of claim 1 , further comprising annealing the semiconductor substrate after implanting second ions to form LDD regions.