Semiconductor device having an arithmetic unit of a reconfigurable circuit configuration in accordance with stored configuration data and a memory storing fixed value data to be supplied to the arithmetic unit, requiring no data area for storing fixed value data to be set in a configuration memory
View Patent ↗A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.
1. A semiconductor device comprising:
a configuration memory storing configuration information;
an arithmetic unit group having a plurality of arithmetic units, and capable of reconfiguring a circuit configuration in accordance with the configuration information supplied from said configuration memory; and
a fixed value memory storing a fixed value to be used in arithmetic processing in said arithmetic unit group, and supplying the stored fixed value to said arithmetic unit group, wherein:
said configuration memory stores, together with the configuration information, fixed value designation information to acquire a fixed value, corresponding to the configuration information, from said fixed value memory.
2. The device according to claim 1 , further comprising:
a fixed value designation information register holding the fixed value designation information read out together with the configuration information from said configuration memory, and supplying the fixed value designation information to said fixed value memory.
3. The device according to claim 1 , wherein the fixed value designation information is address information of said fixed value memory, which indicates an area in which a fixed value corresponding to the configuration information is stored.
4. The device according to claim 1 , further comprising a selector selectively supplying, to said arithmetic unit group, a fixed value supplied from said fixed value memory or an input value different from the fixed value, in accordance with the configuration information.
5. The device according to claim 4 , wherein said selector is placed between said arithmetic unit group and a bus connected to said arithmetic unit group, and selectively supplies, to said arithmetic unit group, a fixed value supplied from said fixed value memory or an input value from said bus.
6. The device according to claim 1 , wherein the semiconductor device comprises a plurality of said arithmetic unit groups, and said fixed value memory is divided into an arbitrary number of memories in accordance with said plurality of arithmetic unit groups.
7. The device according to claim 1 , wherein the semiconductor device comprises a plurality of said arithmetic unit groups and a plurality of said fixed value memories, and each of said plurality of arithmetic unit groups receives supply of a fixed value from one of said plurality of fixed value memories.
8. The device according to claim 7 , wherein said configuration memory stores, together with the configuration information, fixed value designation information related to each fixed value memory and used to acquire, from said plurality of fixed value memories, a fixed value corresponding to the configuration information.
9. The device according to claim 1 , wherein processing functions of said arithmetic units of said arithmetic unit group and an interconnection connecting said arithmetic units are changed in accordance with the configuration information.
10. The device according to claim 1 , further comprising a sequencer controlling a change in circuit configuration of said arithmetic unit group, and managing a state of said arithmetic unit group.