IP Library Granted Patent US 8,230,133
Granted Patent B2
US 8,230,133 · App. 11/036,332 · Granted Jul 24, 2012

Microcomputer with internal DMA

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,230,133
App. No.
11/036,332
Granted
Jul 24, 2012
Kind
B2
Abstract

A microcomputer has: a CPU; memory; a direct memory access controller which controls access to the above memory without passing through the CPU; a plurality of peripheral resources, each having prescribed functions corresponding to a given real resource number, and issuing an access request to the direct memory access controller to perform data transfer with the memory; and, a resource conversion unit, which performs signal conversion between the direct memory access controller and the plurality of peripheral resources. A portion of the peripheral resources among the plurality of peripheral resources are associated with logical resource numbers of the direct memory access controller by the resource conversion unit.

Claims (42)

1. A microcomputer, comprising:

a CPU;

a memory connected to the CPU via a CPU bus;

a direct memory access controller, connected to the CPU via the CPU bus, which controls access to the memory without passing through the CPU;

a plurality of peripheral resources, each assigned a real resource number, configured to transmit an access request to the direct memory access controller to perform data transfer with the memory, and configured to perform a prescribed function in response to a control signal from the direct access memory controller together with the assigned real resource number; and

a resource conversion unit, provided between the direct memory access controller and the plurality of peripheral resources, and including a real to logical correspondence table which associates the real resource numbers of the peripheral resources with logical resource numbers of the direct memory access controller,

wherein the plural peripheral resources are assigned a repeated given real resource number,

wherein the real to logical correspondence table is rewritable, and

wherein the resource conversion unit, based on the real to logical correspondence table, converts the logical resource number data supplied by the direct memory access controller into real resource number data of the portion of peripheral resources, and the converted real resource number data is supplied to the peripheral resources.

2. The microcomputer according to claim 1 , wherein unique physical resource numbers are assigned to each of the plurality of peripheral resources, and the logical resource numbers are associated with the physical resource numbers of the portion of peripheral resources in the real to logical correspondence table.

3. The microcomputer according to claim 1 , wherein the resource conversion unit has a request conversion portion which, based on the real to logical correspondence table, converts a first access request signal supplied by the portion of peripheral resources into a second access request signal corresponding to the logical resource number of the direct memory access controller, and wherein the converted second access request signal is supplied to the direct memory access controller.

4. The microcomputer according to claim 1 , wherein the resource conversion unit has a clear request conversion portion which, based on the real to logical correspondence table, converts a first clear request signal to cancel an access request, supplied by the direct memory access controller, into a second clear request signal to the single corresponding peripheral resource among the portion of peripheral resources, and wherein the converted second clear request signal is supplied to the single corresponding peripheral resource.

5. The microcomputer according to claim 1 , wherein the resource conversion unit has a clear request conversion portion which, based on the real to logical correspondence table, converts a first clear request signal, corresponding to the logical resource number and supplied by the direct memory access controller, to cancel the access request into a second clear request signal to a single corresponding peripheral resource among the portion of peripheral resources, and wherein the converted second clear request signal is supplied to the single corresonding peripheral resource.

6. The microcomputer according to claim 1 , further having a debug support unit which is accessible by an external device, and wherein the debug support unit overwrites correspondences in the real to logical correspondence table in response to control by the external device.

7. The microcomputer according to claim 1 , further having a debug support unit which is accessible by an external device, and wherein the debug support unit, in response to control by the external device, overwrites correspondences in the real to logical correspondence table.

8. A microcomputer, comprising:

a CPU;

a memory connected to the CPU via a CPU bus;

a direct memory access controller, connected to the CPU via the CPU bus, which controls access to the memory without passing through the CPU;

a plurality of peripheral resources, each being assigned a real resource number, configured to transmit an access request signal to the direct memory access controller to perform data transfer with the memory, and configured to cancel such access request signal in response to receiving a clear request signal supplied by the direct memory access controller and the assigned real resource number; and

a resource conversion unit, provided between the direct memory access controller and the plurality of peripheral resources, and including a first correspondence table that associates a portion of the peripheral resources among the plurality of peripheral resources with logical resource numbers of the direct memory access controller, the resource conversion unit to perform conversion of the access request signal and clear request signal between the direct memory access controller and the plurality of peripheral resources, based on the first correspondence table;

wherein the first correspondence table is rewritable by an external device,

wherein the plural peripheral resources are assigned a repeated given real resource number,

wherein the resource conversion unit includes a second correspondence table configured to indicate correspondences between real resource numbers of the portion of peripheral resources and the logical resource numbers, the second correspondence table is rewritable, and

wherein the resource conversion unit includes a resource number conversion portion which, based on the second correspondence table, converts logical resource number data supplied by the direct memory access controller into real resource number data of the portion of peripheral resources, and supplies the converted real resource number data to the portion of peripheral resources.

9. The microcomputer according to claim 8 , wherein:

the resource conversion unit includes a request conversion portion which, based on the first correspondence table, converts a first access request signal supplied by the portion of peripheral resources into a second access request signal corresponding to the logical resource number of the direct memory access controller, and supplies the converted second access request signal to the direct memory access controller; and

the resource conversion unit includes a clear request conversion portion which, based on the first correspondence table, converts a first clear request signal to cancel an access request, supplied by the direct memory access controller, into a second clear request signal to a corresponding single peripheral resource among the portion of peripheral resources, and supplies the converted second clear request signal to the single corresponding peripheral resource.

10. A microcomputer, comprising:

a CPU;

a memory connected to the CPU via a CPU bus;

a direct memory access controller, connected to the CPU via the CPU bus, which controls access to the memory;

a plurality of peripheral resources, each including a repeated real resource number, configured to transmit an access request to the direct memory access controller to perform data transfer with the memory, and configured to perform a prescribed function in response to a control signal from the direct access memory controller together with the assigned real resource number; and

a resource conversion unit, provided between the direct memory access controller and the plurality of peripheral resources, and including a first correspondence table that associates the real resource numbers of the peripheral resources with logical resource numbers of the direct memory access controller,

wherein the resource conversion unit converts the logical resource number generated by the direct memory access controller into the real resource number, based on the first correspondence table.

11. A microcomputer, comprising:

a CPU;

a memory connected to the CPU via a CPU bus;

a direct memory access controller, connected to the CPU via the CPU bus, configured to control access to the memory;

a plurality of peripheral resources, each including a repeated real resource number and being configured to transmit an access request signal to the direct memory access controller in order to perform data transfer with the memory and to perform a prescribed function in response to a control signal from the direct access memory controller together with the assigned real resource number; and

a resource conversion unit, provided between the direct memory access controller and the plurality of peripheral resources, including a first correspondence table that associates the real resource numbers of the peripheral resources with logical resource numbers of the direct memory access controller, the resource conversion unit configured to convert the logical resource number generated by the direct memory access controller into the real resource number.

12. The microcomputer according to claim 1 , wherein the direct memory access controller includes four channels and two-bit logical resource numbers are provided in the direct memory access controller corresponding to these four channels.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2005
From: USUI, MINORU
To: FUJITSU LIMITED
Reel/Frame 016198/0130 →