IP Library Granted Patent US 7,180,170
Granted Patent B2
US 7,180,170 · App. 11/040,334 · Granted Feb 20, 2007

Lead-free integrated circuit package structure

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Quick Facts
Patent No.
US 7,180,170
App. No.
11/040,334
Granted
Feb 20, 2007
Kind
B2
Abstract

An integrated circuit package ( 60 ) has a substrate ( 12 ) with a first surface ( 51 ) for mounting a semiconductor die ( 20 ) and a second surface ( 52 ) defining a via ( 70 ). A lead ( 26 ) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

Claims (25)

1. An integrated circuit package, comprising:

a substrate having a first surface for mounting a semiconductor die and a second surface defining a via; and

a lead-free lead formed with a conductive material to project outwardly from the second surface, where the conductive material is extended from the lead-free lead and through the via for coupling to the semiconductor die, and wherein the lead-free lead in non-spherical shape.

2. The integrated circuit package of claim 1 , wherein the via is formed through the substrate to the first surface.

3. The integrated circuit package of claim 2 , wherein the conductive material extends along the first surface to form a pad for electrically coupling to the semiconductor die.

4. The integrated circuit package of claim 1 , wherein the conductive material is disposed along the second surface from the via to the lead.

5. The integrated circuit package of claim 1 , wherein the conductive material includes copper.

6. The integrated circuit package of claim 5 , wherein the conductive material includes plated copper.

7. The integrated circuit package of claim 1 , wherein the lead-free lead projects from the second surface a distance of at least fifty micrometers.

8. The integrated circuit package of claim 1 , wherein the substrate is formed with a dielectric material.

9. The integrated circuit of claim 8 , wherein the dielectric material includes bismaleimide-triazine resin.

10. An integrated circuit, comprising:

a semiconductor die;

a substrate having first surface for mounting the semiconductor die and a second surface defining a via;

a signal path formed with a first material that is disposed along the first surface and through the via to route a signal between the second surface and the semiconductor die; and

a lead-free lead formed with the first material for coupling to the signal path, where the lead-free lead projects a distance from the second surface for receiving the signal, and wherein the lead-free lead comprises a nonspherical shape with a columnar grain structure.

11. The integrated circuit of claim 10 , wherein the substrate is formed with a second material.

12. The integrated circuit of claim 11 , wherein the first material comprises a conductive material and the second material comprises an insulator.

13. The integrated circuit of claim 10 , wherein the signal path extends along the first surface to form a pad, further comprising a bonding wire for coupling the signal from the pad to the semiconductor die.

14. The integrated circuit of claim 10 , wherein the signal path is routed along the second surface to form an access pad for disposing the lead.

15. The integrated circuit of claim 14 , wherein the access pad is formed with a first thickness of the conductive material and the lead is formed with a second thickness of the conductive material.

16. The integrated circuit of claim 14 , wherein the signal path is extended along the second surface and the lead is projected from a surface of the access pad.

17. The integrated circuit of claim 10 , wherein the distance is from about fifty micrometers to about one hundred twenty-five micrometers.

18. The integrated circuit of claim 17 , wherein the lead-free lead comprises plated copper.

19. The integrated circuit of claim 10 further including a solder mask formed on the second surface.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →