Patent Assignment
Reel/Frame 033686/0092
Release of Security Interest
Recorded: 2014-09-04
Pages: 21
Assignor
JPMORGAN CHASE BANK, N.A.
Executed: 2010-05-11
Assignee
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
5005 EAST MCDOWELL ROAD, MD-A700, PHOENIX, ARIZONA, 85008
Covered Properties
(169)
Method of Forming a Diode for Integration with a Semiconductor Device and Method of Forming a Transistor Device Having an Integrated Diode
Patent:
6,773,977 →
Application:
09/715,748 →
Method of Forming a Semiconductor Device and Structure Therefor
Patent:
6,549,156 →
Application:
10/122,169 →
Method of Making a Semiconductor Device with a Low Permittivity Region
Patent:
6,531,376 →
Application:
10/123,657 →
Method of Forming a Semiconductor Device and Structure Therefor
Patent:
6,613,622 →
Application:
10/194,165 →
Method of Forming a Semiconductor Device and Structure Therefor
Patent:
6,589,845 →
Application:
10/195,166 →
Method of Forming a Low Voltage Semiconductor Storage Device and Structure Therefor
Patent:
6,654,312 →
Application:
10/228,399 →
Method of Forming a Voltage Detection Device and Structure Therefor
Patent:
6,605,978 →
Application:
10/254,274 →
Buffer Circuit with Programmable Switching Thresholds
Ldmos Transistor with Enhanced Termination Region for High Breakdown Voltage with Low On-Resistance
Hybrid Regulator with Switching and Linear Sections
Method of Forming a Power System and Structure Therefor
Low Voltage Transient Voltage Suppressor and Method of Making
Method of Forming a Low Quiescent Current Voltage Regulator and Structure Therefor
Method of forming a body contact of a transistor and structure therefor
Method of Forming a Protection Circuit and Structure Therefor
Patent:
6,781,502 →
Application:
10/429,399 →
High Speed Receiver with Wide Input Voltage Range
Power Factor Correction Method with Zero Crossing Detection and Adjustable Stored Reference Voltage
Patent:
6,756,771 →
Application:
10/465,733 →
Method of Forming a Reference Voltage and Structure Therefor
Power Factor Correction Circuit and Method of Varying Switching Frequency
Semiconductor Device with Wire Bond Inductor and Method
Low Audible Noise Power Supply Method and Controller Therefor
Method of Marking a Low Profile Packaged Semiconductor Device
Power Supply Controller Method and Structure
Negative Current Compensation Method and Circuit
Direct Chip Attach Structure and Method
Vertical Compound Semiconductor Field Effect Transistor Structure
Patent:
6,818,939 →
Application:
10/623,397 →
Semiconductor Device and Method of Providing Regions of Low Substrate Capacitance
Patent:
6,818,525 →
Application:
10/632,636 →
Method of Forming a Wide Bandwidth Differential Amplifier and Structure Therefor
Lead-Free Integrated Circuit Package Structure
High Voltage Sensor Device and Method Therefor
Cross-Talk Reduction Circuit and Method Therefor
Integrated Semiconductor Inductor and Method Therefor
Delay Circuit and Method Therefor
Semiconductor Device Edge Termination Structure
Superjunction Semiconductor Device Structure
Semiconductor Device Having Deep Trench Charge Compensation Regions and Method
Translator Circuit and Method Therefor
Schottky Diode and Method of Manufacture
Schottky Diode and Method of Manufacture
Fan Out Buffer and Method Therefor
Bi-Directional Transistor and Method Therefor
Method of Forming an Integrated Power Device and Structure
Semiconductor Device Having Enhanced Performance and Method
Semiconductor Device Having Field Stabilization Film and Method
Ldmos Transistor with Enhanced Termination Region for High Breakdown Voltage with On-Resistance
Power Switch Structure with Low Rdson and Low Current Limit and Method
Voltage Sense Circuit and Method Therefor
Semiconductor Device Having Screening Electrode and Method
Power Semiconductor Device Having Improved Performance and Method
Method of Forming a Semiconductor Device and Structure Therefor
Semiconductor Device Having Trench Structures and Method
Method for Regulating an Output Signal and Circuit Therefor
Secondary Side Controller and Method Therefor
Method of Forming an in-Rush Limiter and Structure Therefor
Power System Inhibit Method and Device and Structure Therefor
Method for Regulating Temperature and Circuit Therefor
Single Pin Multi-Function Signal Detection Method and Structure Therefor
Power Supply Controller and Method Therefor
Power Overload Detection Method and Structure Therfor
Current Regulator and Method Therefor
Semiconductor Structure with Improved on Resistance and Breakdown Voltage Performance
Semiconductor Structure with Improved on Resistance and Breakdown Voltage Performance
Multi-Current Battery Charger Circuit and Method Therefor
Semiconductor component and method of manufacture
Application:
11/202,965 →
Publication:
US 2007/0035019
Method of Forming a Start-Up Device and Structure Therefor
Encapsulated Chip Scale Package Having Flip-Chip on Lead Frame Structure and Method
Method of Forming an Integrated Voltage Protection Device and Structure
Method of Forming a Low Resistance Semiconductor Contact and Structure Therefor
Method of Forming a Self-Aligned Transistor
Method of Forming a Molded Array Package Device Having an Exposed Tab and Structure
Method of Forming a Trench Semiconductor Device and Structure Therefor
Method of Forming a Leaded Molded Array Package
Method of Forming a Power Supply Controller and Device Therefor
Diagnostic Circuit and Method Therefor
Semiconductor Package Structure and Method of Manufacture
Semiconductor component and method of manufacture
Application:
11/281,160 →
Publication:
US 2007/0117259
Output Amplifier Structure with Bias Compensation
Semiconductor Device and Method of Providing Regions of Low Substrate Capacitance
Multi-Phase Power Supply Controller and Method Therefor
Encapsulated Electronic Device Structure
Semiconductor Package Structure for Vertical Mount and Method
Thyristor and Method of Manufacture
Patent:
7,205,583 →
Application:
11/317,213 →
Thyristor and Method of Manufacture
Fault Control Circuit and Method Therefor
Switching Power Supply Controller with Improved Effeciency and Method Therefor
Power Supply Controller and Method Therefor
Schottky Diode Structure with Enhanced Breakdown Voltage and Method of Manufacture
Method of Forming a Floating Charge Pump and Structure Therefor
Method for Nullifying Temperature Dependence and Circuit Therefor
Bi-Directional Transistor with by-Pass Path and Method Therefor
Method of Forming an Mos Transistor and Structure Therefor
Power Semiconductor Device Having Improved Performance and Method
Method of Forming an Eprom Cell and Structure Therefor
Led Control Circuit and Method Therefor
Semiconductor Package Structure and Method of Manufacture
Linear Regulator and Method Therefor
Shunt Protection Circuit and Method Therefor
Dishwasher
Application:
11/422,733 →
Publication:
US 2006/0278258
Circuit and Mathod for Regulating Voltage
Application:
11/424,222 →
Publication:
US 2007/0290657
Circuit and Method for Reducing Electromagnetic Interference
Method for Inhibiting Thermal Run-Away
Accurate Timing Generator and Method Therefor
Semiconductor Device Having Sub-Surface Trench Charge Compensation Regions
Method of Forming a Voltage Regulator and Structure Therefor
Semiconductor Filter Structure and Method of Manufacture
Filter Having Integrated Floating Capacitor and Transient Voltage Suppression Structure and Method of Manufacture
Method of Forming a Schottky Diode and Structure Therefor
Semiconductor Package Structure and Method of Manufacture
Application:
11/466,539 →
Publication:
US 2008/0054420
Semiconductor Package Structure Having Multiple Heat Dissipation Paths and Method of Manufacture
Semiconductor Package and Method Therefor
Method of forming a feedback network and structure therefor
Application:
11/474,472 →
Publication:
US 2007/0296384
Method of Forming a Programmable Voltage Regulator and Structure Therefor
Method of Forming a Secondary-Side Controller and Structure Therefor
Power Factor Correction Circuit and Method Therefor
Multilayer Gettering Structure for Semiconductor Device and Method
Integrated Filter Having Ground Plane Structure
Semiconductor Package and Leadframe Therefor Having Angled Corners
Semiconductor Device and Method of Producing High Contrast Identification Mark
Dc-Dc Converter and Method
Led Controller and Method Therefor
Method of Forming a Semiconductor Device Having Trench Charge Compensation Regions
Compensated Switching Power Supply Controller and Method Therefor
Protection Circuit and Method Therefor
Power Supply Controller and Method Therefor
Method of Forming a Power Supply Controller and Structure Therefor
Charge Pump Circuit and Method Therefor
Battery Protection Method and Circuit Therefor
Class-D Amplifier and Method Therefor
Method for Regulating a Voltage and Circuit Therefor
Dc-Dc Converter Controller Having Optimized Load Transient Response and Method Thereof
Method of Testing a Power Supply Controller and Structure Therefor
High Accuracy Zero Crossing Detector and Method Therefor
Switched Capacitor Controller and Method Therefor
Power Supply Soft Start Controller with No Output Voltage Undershoot When Transistioning from Skip Cycle Mode to Normal Mode
Method of Forming a Signal Level Translator and Structure Therefor
Electronic Package Having Down-Set Leads and Method
Method for Regulating a Voltage and Circuit Therefor
Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics
Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics
Dc-To-Dc Converter and Method Therefor
Soft-Start Circuit and Method Therefor
Semiconductor Device Having Deep Trench Charge Compensation Regions and Method
Voltage Reference Circuit and Method Therefor
Semiconductor Component and Method of Manufacture
Method of Forming an Operational Amplifier and Structure Therefor
Semiconductor Device Having Reduced Gate Charge and Reduced on Resistance and Method
Semiconductor Component and Method of Manufacturing
Method of Forming an Over-Voltage Protection Circuit and Structure Therefor
Semiconductor Device Having Trench Edge Termination Structure
Method of Forming a Low Capacitance Semiconductor Device and Structure Therefor
Multi-Chip Semiconductor Connector and Method
Multi-Chip Semiconductor Connector Assembly Method
Led Control System
Semiconductor Component and Method of Manufacture
Schottky Diode Structure with Multi-Portioned Guard Ring and Method of Manufacture
Accurate Voltage Reference Circuit and Method Therefor
Power System Inhibit Method and Device and Structure Therefor
Semiconductor Component and Method of Manufacture
Parameter Control Circuit Including Charging and Discharging Current Mirrors and Method Therefor
Semiconductor Component and Method of Manufacture
Tuning Circuit and Method
Application:
11/749,038 →
Publication:
US 2008/0284526
Method of Forming a Pwm Controller and Structure Therefor
Edge Seal for a Semiconductor Device and Method Therefor
Schottky Diode and Method Therefor
Method of Forming a Transistor Diagnostic Circuit
Circuit Component and Method of Manufacture
Encapsulated Electronic Device
Semiconductor Device Having Trench Structures and Method
Packaged Semiconductor Device
Patent:
489,338 →
Application:
29/187,122 →
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Assignment of Assignor's Interest
Apr 11, 2016
From: ROBB, FRANCINE Y.; PEARSE, JEFFREY; HEMINGER, DAVID M.; ROBB, STEPHEN P.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038247/0862 →
Security Interest
Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
Corrective Assignment to Correct the Incorrect Patent Number 5859768 and to Recite Collateral Agent Role of Receiving Party in the Security Interest Previously Recorded on Reel 038620 Frame 0087. Assignor(S) Hereby Confirms the Security Interest.
Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
Release of Security Interest in Patents Recorded at Reel 038620, Frame 0087
Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →