Semiconductor structure with improved on resistance and breakdown voltage performance

1. A method for forming a lateral IGFET device comprising the steps of:

providing a semiconductor substrate having a drift region of a first conductivity type, wherein the semiconductor substrate comprises a second conductivity type;

forming a body region of the second conductivity type adjacent the drift region;

forming a drain contact region of the first conductivity type adjacent the drift region;

forming spaced apart trenches in the drift region between the drain contact and the body region;

doping sidewall and lower surfaces of the spaced apart trenches with a dopant of the first conductivity type to form first doped regions within the drift region, wherein the first doped regions have a higher doping concentration than the drift region;

doping the sidewall and lower surfaces of the spaced apart trenches with a dopant of the second conductivity type to form second doped regions within the first doped regions, wherein each trench has a first doped region and a second doped region wrapped around its lower surface;

filling the spaced apart trenches with a material;

forming a source region of the first conductivity type in the body region; and

forming a gate structure adjacent to the body region.

2. The method of claim 1 , wherein the step of filling the spaced apart trenches with a material includes filling the trenches with one of an oxide, semi-insulating polycrystalline silicon, or polycrystalline silicon.

3. The method of claim 1 , wherein the step of doping the sidewall and lower surfaces of the trenches with a dopant of the first conductivity type includes doping the sidewall and lower surfaces of the spaced apart trenches with the dopant of the first conductivity type wherein the first doped regions are spaced apart within the drift region.

4. The method of claim 3 , wherein the step of doping the sidewall and lower surfaces includes doping the sidewall and lower surfaces of the spaced apart trenches with the dopant of the first conductivity type wherein the first doped regions are spaced apart from the semiconductor substrate.

5. The method of claim 1 , wherein the step of doping the sidewall and lower surfaces of the spaced apart trenches with a dopant of the first conductivity type includes doping the sidewall and lower surfaces of the trenches with the dopant of the first conductivity type, and wherein the first doped regions are merged together within the drift region.

6. The method of claim 5 , wherein the step of doping the sidewall and lower surfaces of the spaced apart trenches with a dopant of the first conductivity type includes doping the sidewall and lower surfaces of the spaced apart trenches with a dopant of the first conductivity type, wherein the first doped regions contact the semiconductor substrate.

7. The method of claim 1 , wherein the step of doping the sidewall and lower surfaces of the spaced apart trenches with a dopant of the first conductivity type includes doping with angled ion implantation with an implant dose between about 2.0×10 13 atoms/cm 2 to about 5.0×10 13 atoms/cm 2 .

8. The method of claim 1 , wherein the step of providing the semiconductor substrate having a drift region includes providing a semiconductor substrate having a drift region comprising an epitaxial layer formed over the semiconductor substrate.

9. The method of claim 1 , further comprising the step of forming a trench gate structure adjacent to the body region.

10. A process for forming an IGFET device comprising the steps of:

providing a semiconductor substrate having a semiconductor region of a first conductivity type;

forming first and second trenches within the semiconductor region;

forming first regions of the first conductivity type adjacent sidewalls and lower surfaces of the first and second trenches;

forming second regions of a second conductivity type adjacent the sidewalls and lower surfaces of the first and second trenches;

placing a material within the first and second trenches to form a super junction structure within the semiconductor layer;

forming a body region or the second conductivity type in the semiconductor substrate adjacent one side of the super junction structure;

forming a drain contact region of the first conductivity type adjacent an opposite side of the super junction structure;

forming a source region of the first conductivity type in the body region; and

forming a gate structure adjacent to the body region.

11. The method of claim 10 , wherein the step of placing the material within the trenches includes placing a material selected from a group consisting of an oxide, semi-insulating polycrystalline silicon, and polycrystalline silicon.

12. The method of claim 10 , wherein the step of forming the first doped regions includes the steps of:

forming first and second grooves in the semiconductor region;

forming an epitaxial region of the first conductivity type within the first and second grooves;

forming the first trench within the first groove, wherein the first trench extends partially into the epitaxial region within the first groove; and

forming the second trench within the second groove, wherein the second trench extends partially into the epitaxial region with in the second groove, and wherein that portion of the epitaxial region around the first and second trenches provides the first doped regions.

13. The method of claim 10 wherein the step of forming the first doped regions includes ion implanting dopant or the first conductivity type.

14. The method of claim 10 wherein the step of forming the second doped regions includes ion implanting dopant of the second conductivity type.

15. The method of claim 10 further comprising the step of forming a trench gate structure adjacent the body region.

16. A lateral IGFET device comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type formed in the drift region;

a drain contact region of the first conductivity type formed in the drift region;

first and second trenches formed in the drift region between the drain contact and the body region;

first doped regions of the first conductivity type formed in sidewall and lower surfaces of the first and second trenches wherein the first doped regions have a higher doping concentration than the drift region;

second doped regions of the second conductivity type formed in the sidewall and lower surfaces of the first and second trenches, wherein both the first and second doped regions are around the lower surfaces of the first and second trenches;

a source region of the first conductivity type formed in the body region; and

a gate structure formed adjacent to the body region.

17. The device of claim 16 , wherein the first and second trenches include a material within them, the material selected from a group consisting of an oxide, semi-insulating polycrystalline silicon, and polycrystalline silicon.

18. The device of claim 16 , wherein the first doped region adjacent the first trench is merged with the first doped region adjacent the second trench within the drift region.

19. The device of claim 16 , wherein the first doped region adjacent the first trench is spaced apart from the first doped region adjacent the second trench.

20. The device of claim 16 further comprising a trench gate structure formed in the drift region.

21. A process for forming a lateral IGFET device comprising the steps of:

forming first and second trenches within a drift region of a first conductivity type at a first surface;

forming first epitaxial layers of the first conductivity type within the first and second trenches, wherein the first epitaxial layers have a doping concentration higher than the semiconductor region;

forming second epitaxial layers of a second conductivity type over the first epitaxial layers within the first and second trenches, wherein the first and second epitaxial layers fill the first and second trenches to provide a super junction structure;

forming a body region of the second conductivity type on one side of the super junction structure adjacent the first surface;

forming a drain contact region of the first conductivity type on an opposite side of the super junction structure adjacent the first surface;

forming a source region of the first conductivity type within the body region; and

forming a gate structure adjacent the body region.

22. The process of claim 21 , wherein the step of forming the gate structure includes forming a trench gate structure.

23. The process of claim 21 further comprising the step of forming trench gate structure adjacent the body region.