IP Library Granted Patent US 7,602,027
Granted Patent B2
US 7,602,027 · App. 11/618,363 · Granted Oct 13, 2009

Semiconductor component and method of manufacture

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Quick Facts
Patent No.
US 7,602,027
App. No.
11/618,363
Granted
Oct 13, 2009
Kind
B2
Abstract

A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Claims (23)

1. A method for manufacturing a semiconductor component, comprising:

providing a substrate, wherein providing the substrate includes forming a resistor from or above the substrate;

forming a capacitor at a first level above the substrate by:

forming a first layer of dielectric material over the substrate;

forming a first layer of conductive material over the first layer of dielectric material, the first layer of conductive material comprising aluminum and having first and second portions;

forming a second layer dielectric material over the first layer of conductive material; and

forming a second layer of conductive material over the second layer of dielectric material, the second layer of conductive material comprising aluminum; and

forming an inductor at a second level above the first level by:

forming a third layer of dielectric material over the second layer of conductive material;

forming at least one damascene opening in the third layer of dielectric material by:

forming a fourth layer of dielectric material on the third layer of dielectric material;

forming a first portion of the at least one damascene opening in the third layer of dielectric material; and

forming a second portion of the at least one damascene opening in the fourth layer of dielectric material, wherein the second portion of the at least one damascene opening exposes a portion of the second layer of conductive material;

forming copper in the at least one damascene opening and further including:

forming an active device from the substrate;

forming an opening in the first layer of dielectric material, the opening exposing the active device;

forming an electrical conductor in the opening;

forming the second portion of the first layer of conductive material on the conductor;

electrically isolating the first portion of the first layer of conductive material from the second portion of the first layer of conductive material; and

forming a trench through the second, third and fourth layers of dielectric material, the trench exposing the second portion of the first layer of conductive material.

2. The method of claim 1 , further including forming a conductive material in the trench.

3. The method of claim 2 , wherein forming the conductive material in the trench includes forming copper in the trench.

4. The method of claim 3 , further including forming aluminum over the copper in the trench.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →