IP Library Granted Patent US 7,642,754
Granted Patent B2
US 7,642,754 · App. 11/448,881 · Granted Jan 5, 2010

Method of forming a voltage regulator and structure therefor

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Quick Facts
Patent No.
US 7,642,754
App. No.
11/448,881
Granted
Jan 5, 2010
Kind
B2
Abstract

In one embodiment, a voltage regulator uses a first current to charge a by-pass capacitor for a first time period and uses a second current after the first time period.

Claims (30)

1. A voltage regulator comprising:

an output configured to regulate an output voltage to a target value;

a first input configured for coupling to a capacitor and coupled to receive a reference signal having a value;

a charging circuit coupled to the first input and configured to charge the capacitor toward the value of the reference signal with a first current during a first time period and to charge the capacitor with a second current after the first time period wherein the first current is greater than the second current; and

an error amplifier coupled to simultaneously receive, during the second time period, the reference signal and a sense signal that is representative of the output voltage, and to responsively regulate the sense signal to approximately equal the reference signal.

2. The voltage regulator of claim 1 wherein the charging circuit includes a timer configured to assert a control signal for the first time period, and an amplifier coupled to receive the control signal and responsively form the first current.

3. The voltage regulator of claim 2 wherein the amplifier includes a pair of two stage transconductance amplifiers each of which drives a driver transistor.

4. The voltage regulator of claim 3 wherein the pair of two stage transconductance amplifiers are connected in a common source configuration.

5. The voltage regulator of claim 3 wherein a first two stage transconductance amplifier has a first input coupled to receive the reference signal, a second input coupled to an output of the amplifier, and an output coupled to a control electrode of a first output transistor; a second two stage transconductance amplifier has a first input coupled to receive the reference signal, a second input coupled to an output of the amplifier, and an output coupled to a control electrode of a second output transistor; the first output transistor includes a first current carrying electrode coupled to receive an input voltage and a second current carrying electrode coupled to the output of the amplifier; and the second output transistor includes a first current carrying electrode coupled to a voltage return and a second current carrying electrode coupled to the output of the amplifier.

6. The voltage regulator of claim 2 wherein the timer is configured to receive an enable signal and responsively assert the control signal.

7. The voltage regulator of claim 1 further including a reference generator configured to form the reference signal and supply the second current.

8. The voltage regulator of claim 7 wherein the reference generator forms another signal that is representative of the reference signal and the charging circuit is coupled to receive the another signal and form the first current.

9. The voltage regulator of claim 1 wherein the voltage regulator is formed on a semiconductor die having no more than six external connection terminals.

10. A method of forming a voltage regulator comprising:

configuring a reference circuit to generate a first reference signal;

configuring the voltage regulator to regulate an output voltage to a target value, to receive a sense signal that is representative of the output voltage, and to regulate the sense signal to be approximately equal to the first reference signal in order to regulate the output voltage to the desired value; and

configuring the voltage regulator to form a second reference signal that is representative of the first reference signal and to charge a reference output of the voltage regulator to the first reference signal at a first current value responsively to both the first and second reference signals for a first time period and to charge the reference output at a second current value responsively to the first reference signal but not the second reference signal for a second period of time.

11. The method of claim 10 wherein configuring the voltage regulator to form the second reference signal includes configuring the voltage regulator to form the first current value to be at least ten times the second current.

12. The method of claim 10 wherein configuring the voltage regulator to form the second reference signal includes configuring a timer to receive an enable signal and responsively assert a control signal for the first time period.

13. The method of claim 10 wherein configuring the voltage regulator to form the second reference signal includes configuring the voltage regulator to charge the reference output responsively to both the first and second reference signals for the first time period faster than the first reference signal can charge the reference output.

14. The method of claim 10 wherein configuring the voltage regulator to form the second reference signal that is representative of the first reference signal includes coupling first and second amplifiers in a common source configuration to form the first current value.

15. The method of claim 14 further including configuring a reference generator to form the first reference signal and couple a third reference signal that is representative of the first reference signal to the first and second amplifiers.

16. The method of claim 10 wherein configuring the voltage regulator to form the second reference signal that is representative of the first reference signal includes configuring the voltage regulator to charge the reference output of the voltage regulator to the first reference signal at the first current value responsively to both the first and second reference signals simultaneously for the first time period wherein the first current value is greater than the second current value.

17. A voltage regulator comprising:

a reference circuit configured to form a first reference signal and a second reference signal that is substantially equal to the first reference signal;

coupling an error amplifier to receive the first reference signal and regulate a voltage output of the voltage regulator to a target voltage value; and

coupling an amplifier to receive the second reference signal and charge a reference output of the voltage regulator substantially to the first reference signal during a first time period.

18. The voltage regulator of claim 17 wherein the amplifier includes two transconductance amplifiers coupled in a common source configuration.

19. The voltage regulator of claim 17 wherein a timer circuit asserts a control signal for the first time period and the amplifier charges the reference output responsively to the control signal.

20. The voltage regulator of claim 17 wherein the amplifier charges the reference output at a first current value for the first time period.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2006
From: DOW, STEPHEN W.; MANAPRAGADA, PRAVEEN; MOELLER, DAVID F.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 017986/0935 →