Semiconductor device having deep trench charge compensation regions and method
View Patent ↗In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
1. A semiconductor device comprising:
a body of semiconductor material; and
a charge compensation region including a trench formed in the body of semiconductor material, wherein the trench comprises:
a first epitaxial layer of a first conductivity type formed overlying sidewalls and a lower surface of the trench;
a first intrinsic layer formed overlying the first epitaxial layer;
a second epitaxial layer of a second conductivity type formed overlying the first intrinsic layer, wherein the first intrinsic layer is formed between the first and second epitaxial layers to reduce intermixing of opposite conductivity type dopants; and
a second intrinsic layer formed overlying the second epitaxial layer.
2. The device of claim 1 wherein the device is configured as an insulated gate field effect transistor further comprising a doped body region formed in the body of semiconductor material and spaced apart from the trench so that the doped body region does not overly the trench.
3. The device of claim 2 further comprising:
a source region formed in the doped body region; and
a gate structure formed adjacent the trench, the doped body region and the source region.
4. The device of claim 3 wherein the gate structure comprises a conductive spacer gate structure formed along a sidewall of a dielectric region overlying the body of semiconductor material.
5. The device of claim 4 wherein the conductive spacer gate structure comprises a doped polysilicon spacer separated from the doped body region and the source region by a dielectric layer.
6. The device of claim 3 further comprising a conductive layer coupled to the charge compensation region.
7. The device of claim 6 further comprising a conductive contact coupled to the source region, and wherein the conductive layer and conductive contact are coupled together.
8. The device of claim 1 wherein the body of semiconductor material comprises:
a semiconductor substrate of a first conductivity type; and
an epitaxial layer formed overlying the semiconductor substrate, and having an upper surface, and wherein the trench extends from the upper surface into the epitaxial layer.
9. The device of claim 8 wherein the epitaxial layer comprises a second conductivity type, and wherein the trench extends from the upper surface into the semiconductor substrate.
10. The device of claim 9 wherein the first conductivity type is n-type, and wherein the second conductivity type is p-type.
11. The device of claim 8 further comprising a doped layer of the first conductivity type formed at the upper surface adjacent the charge compensation region.
12. The device of claim 11 further comprising a doped layer of a second conductivity type formed adjacent the doped layer of the first conductivity type.
13. A semiconductor device comprising:
a body of semiconductor material having first and second opposing major surfaces;
a first doped region formed in the body of semiconductor material adjacent the first major surface and comprising a first conductivity type;
a second doped region formed in the first doped region and comprising a second conductivity type;
a charge compensating trench region formed in the body of semiconductor material adjacent the first doped region, wherein the charge compensating trench region comprises:
a trench;
a first epitaxial semiconductor layer of the second conductivity type formed adjoining surfaces of the trench;
a first intrinsic layer formed overlying the first semiconductor layer;
a second epitaxial semiconductor layer of the first conductivity type formed adjacent the first semiconductor layer, wherein the first intrinsic layer is formed between the first and second epitaxial layers to reduce intermixing of opposite conductivity type dopants;
a second intrinsic layer formed overlying the second semiconductor layer; and
a control electrode formed adjacent the first and second doped regions.
14. The device of claim 13 further comprising a conductive layer coupled to the charge compensating trench region.
15. The device of claim 14 further comprising a third doped region formed in the charge compensating trench and configured to enhance ohmic contact between the conductive layer and the charge compensating trench.
16. The device of claim 13 wherein the control electrode comprises a spacer gate structure.
17. A semiconductor device comprising:
a body of semiconductor material having first and second opposing major surfaces;
a trench formed in the body of semiconductor material;
a first epitaxial semiconductor layer of a first conductivity type formed adjoining surfaces of the trench;
a second epitaxial semiconductor layer of a second conductivity type formed adjacent to the first semiconductor layer to form a charge compensating trench region;
a first buffer semiconductor layer between the first and second epitaxial semiconductor layers, wherein the first buffer layer is configured to reduce intermixing of dopants between the first and second semiconductor layers;
a second buffer semiconductor layer formed overlying the second epitaxial semiconductor layer;
a first doped region in the body of semiconductor material adjacent the charge compensating trench region, wherein the first doped region comprises the second conductivity type;
a second doped region in the first doped region and comprising the first conductivity type; and
a control electrode adjacent the first and second doped regions.
18. The device of claim 17 , wherein the body of semiconductor material comprises a semiconductor substrate of the first conductivity type and a region of semiconductor material of the second conductivity type formed overlying the semiconductor substrate.
19. The device of claim 17 further comprising a conductive layer coupled to the charge compensating trench region and configured to reduce capacitance between the control electrode and the body of semiconductor material when the device is in operation.
20. The device of claim 19 further comprising a third doped region formed in the charge compensation trench region to enhance ohmic contact between the conductive layer and the charge compensation trench region.