Semiconductor package structure and method of manufacture
View Patent ↗In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.
1. A semiconductor package structure device comprising:
a substrate having a major surface;
an electronic chip attached to one portion of the major surface;
a porous matrix of particles bonded to other portions of the major surface; and
an encapsulation layer covering the substrate, wherein the encapsulation layer is within the porous matrix or particles, wherein the porous matrix of particles is configured for enhancing adhesion between the substrate and the encapsulation layer.
2. The structure of claim 1 wherein the substrate comprises:
a conductive flag where the electronic chip is attached; and
a plurality of conductive leads in spaced relationship with the conductive flag, and wherein the porous matrix of particles is bonded to portions of the conductive flag.
3. The structure of claim 2 wherein the porous matrix of particles is bonded to portions of the plurality of conductive leads.
4. The structure of claim 2 further comprising conductive connective portions electrically coupling the electronic chip to the plurality of leads.
5. The structure of claim 4 , wherein the conductive connective structures comprise wire bonds.
6. The structure of claim 4 , wherein the conductive connective structures comprise clips.
7. The structure of claim 1 wherein the encapsulation layer comprises an epoxy mold compound.
8. The structure of claim 1 , wherein the porous matrix or particles comprises a layer of particles having irregular shapes and diameters in a range from about 2.0×10 −6 meters to about 2.5×10 −5 meters.
9. The structure of claim 1 wherein the substrate comprises copper.
10. The structure of claim 1 wherein the porous matrix of particles comprises a metal.
11. The structure of claim 10 , wherein the porous matrix of particles comprises copper.
12. The structure of claim 10 , wherein the porous matrix of particles comprises nickel.
13. A semiconductor packaged device comprising:
a conductive die attach paddle having a first major surface;
conductive leads having a second major surface, wherein the conductive leads are in proximity to the conductive die attach paddle;
a semiconductor device attached to a portion of the first major surface;
conductive connective structures electrically coupling the semiconductor device to the conductive leads;
a porous matrix of particles bonded to other portions of the first major surface; and
a plastic encapsulating layer formed over the conductive die attach paddle and the semiconductor device, wherein the porous matrix of particles engages the plastic encapsulating layer thereby enhancing adhesion between the conductive die attach paddle and the plastic encapsulating layer.
14. The device of claim 13 , wherein the porous matrix or particles is further bonded to portions of the second major surface, wherein the porous matrix of particles further enhances adhesion between the conductive leads and the plastic encapsulating layer.
15. The device of claim 13 , wherein the porous matrix of particles comprises a layer of irregular shaped metal particles having diameters in a range from about 2.0×10 −6 meters to about 2.5×10 −5 meters.
16. The device of claim 13 , wherein the conductive connective structures comprise wire bonds and clips.
17. The device of claim 13 wherein the porous matrix of particles comprise copper.
18. The structure of claim 1 , wherein the porous matrix of particles comprises a ceramic.
19. The structure of claim 18 , wherein the porous matrix of particles comprises a nickel ceramic.