IP Library Granted Patent US 7,297,603
Granted Patent B2
US 7,297,603 · App. 11/093,381 · Granted Nov 20, 2007

Bi-directional transistor and method therefor

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Quick Facts
Patent No.
US 7,297,603
App. No.
11/093,381
Granted
Nov 20, 2007
Kind
B2
Abstract

In one embodiment, a transistor is formed to conduct current in both directions through the transistor.

Claims (26)

1. A method of forming a bi-directional transistor comprising:

forming a first MOS transistor on a semiconductor substrate of a first conductivity type;

forming a body region of the first MOS transistor as a first doped region of a first conductivity and a first doping concentration on a surface of the semiconductor substrate and isolated from a first current carrying electrode region of the first MOS transistor by a first P-N junction and isolated from a second current carrying electrode region of the first MOS transistor by a second P-N junction;

forming a source region of the first MOS transistor as a second doped region of a second conductivity type and a second doping concentration that is overlying a portion of the body region;

forming a third doped region of the second conductivity type between the source region and the body region; and

forming a second MOS transistor coupled to selectively couple the body region of the first MOS transistor to the first current carrying electrode of the first MOS transistor.

2. The method of claim 1 further including forming the second MOS transistor electrically coupled between the body region of the first MOS transistor and the first current carrying electrode region of the first MOS transistor.

3. The method of claim 1 wherein the first MOS transistor is a vertical transistor and the second MOS transistor is a lateral MOS transistor formed on the semiconductor substrate.

4. The method of claim 1 wherein the first MOS transistor is a vertical transistor and the second MOS transistor is a vertical MOS transistor formed on the semiconductor substrate.

5. The method of claim 1 further including a third MOS transistor coupled to selectively couple the body region of the first MOS transistor to a second current carrying electrode of the first MOS transistor.

6. The method of claim 1 wherein forming the third doped region of the second conductivity type includes forming the third doped with a third doping concentration that is less than the second doping concentration.

7. A method of forming a bi-directional transistor comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first doped region of a second conductivity type on a surface of the semiconductor substrate as a body region of a first transistor;

forming a second doped region of the first conductivity type within the first doped region and extending a first distance into the first doped region as a first current carrying electrode region of the first transistor; and

forming a third doped region of the first conductivity type and extending from the second doped region a second distance into the first doped region.

8. The method of claim 7 further including forming a fourth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region; forming a source and a drain of a second transistor in the fourth doped region; and coupling the second transistor electrically between the first doped region and the semiconductor substrate.

9. The method of claim 8 wherein forming the source and the drain of the second transistor in the fourth doped region includes forming a fifth doped region within the fourth doped region; forming a sixth doped region within the fourth doped region and spaced apart from the fifth doped region; electrically coupling the fifth doped region to the first doped region; and coupling the sixth doped region to the semiconductor substrate.

10. The method of claim 7 further including forming a fourth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region; forming a source and a drain of a second transistor in the fourth doped region; and coupling the second transistor electrically between the first doped region and the second doped region.

11. The method of claim 10 wherein forming the source and the drain of the second transistor in the fourth doped region includes forming a fifth doped region within the fourth doped region; forming a sixth doped region within the fourth doped region and spaced apart from the fifth doped region; electrically coupling the fifth doped region to the first doped region; and coupling the sixth doped region to the second doped region.

12. The method of claim 7 wherein forming the first doped region of the second conductivity type on the surface of the semiconductor substrate as the body region of the first transistor includes forming the first transistor as a vertical transistor.

13. A method of forming a bi-directional transistor comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first doped region of a second conductivity type on a surface of the semiconductor substrate as a body region of a first transistor;

forming a second doped region of the first conductivity type having a first doping concentration within the first doped region and extending a first distance into the first doped region as a first current carrying electrode region of the first transistor; and

forming a third doped region of the first conductivity type having a second doping concentration that is less than the first doping concentration and extending from the second doped region a second distance into the first doped region wherein the second distance is greater than the first distance.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2005
From: ROBB, STEPHEN P.; ROBB, FRANCINE Y.; HIGHTOWER, ROBERT F.
To: SEMICONDUCTOR COMPONENTS INDUSTERIS, L.L.C.
Reel/Frame 016441/0155 →