Semiconductor package and method therefor
View Patent ↗In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
1. A method of forming a semiconductor package comprising:
forming a die attach area on an intermediate substrate;
forming a first plurality of connection terminals on the intermediate substrate;
forming a tamper barrier on the intermediate substrate wherein the first plurality of connection terminals is between the tamper barrier and the die attach area;
attaching a semiconductor die to the die attach area and electrically connecting connection points on the semiconductor die to the first plurality of connection terminals;
encapsulating the semiconductor die and at least a portion of surfaces of both the first plurality of connection terminals and the tamper barrier wherein the tamper barrier is positioned between an edge of the semiconductor package and the first plurality of connection terminals and wherein a length of the tamper barrier is greater than a total width of all of the plurality of connection terminals plus an inner terminal spacing of the plurality of connection terminals; and
removing the intermediate substrate.
2. The method of claim 1 wherein attaching the semiconductor die to the die attach area and electrically connecting connection points on the semiconductor die includes not electrically connecting the tamper barrier to the semiconductor die.
3. The method of claim 1 wherein forming the tamper barrier includes forming a conductor extending adjacent to the edge of the semiconductor package.
4. The method of claim 1 wherein forming the tamper barrier includes forming the first plurality of connection terminals symmetrically to a center of the semiconductor package and forming the tamper barrier asymmetrically to the center of the semiconductor package.
5. A method of forming a semiconductor package comprising:
forming a plurality of connection terminals on a first major surface of the semiconductor package wherein the plurality of connection terminals are positioned symmetrically to a center of the first major surface; and
forming a tamper barrier to extend continuously between the plurality of connection terminals and a first edge of the semiconductor package wherein the tamper barrier is asymmetrical to the semiconductor package.
6. The method of claim 5 wherein forming the tamper barrier includes forming the tamper barrier adjacent to an edge of the first major surface.
7. The method of claim 5 wherein forming the tamper barrier adjacent to the first edge of the semiconductor package includes forming of the tamper barrier as a portion of the semiconductor package that extends at an angle a first distance away from the first major surface wherein the first distance is greater than a distance that any of the plurality of connections terminals extend from the first major surface.
8. The method of claim 5 wherein forming the tamper barrier includes forming the tamper barrier with a length that is greater than a width of the plurality of connection terminals plus the inner terminal spacing of the plurality of connection terminals.
9. The method of claim 5 wherein forming the tamper barrier includes forming a conductor as the tamper barrier.
10. A method of forming a semiconductor package comprising:
forming a plurality of connection terminals on a first major surface of the semiconductor package wherein at least a portion of the plurality of connection terminals are electrically connected to a semiconductor die within the semiconductor package; and
forming a tamper barrier between at least a portion of the plurality of connection terminals and a first edge of the semiconductor package wherein the tamper barrier extends at a first angle a first distance away from the first major surface wherein the first distance is greater than a distance that any of the plurality of connection terminals extends away from the first major surface.
11. The method of claim 10 including forming the tamper barrier as a portion of an encapsulation material used for forming a body of the semiconductor package and wherein the first angle is one of an acute angle, a perpendicular angle, or an obtuse angle.
12. The method of claim 1 wherein forming the tamper barrier includes positioning the tamper barrier no greater than approximately 0.1 mm from the first plurality of connection terminals.
13. The method of claim 10 wherein forming the tamper barrier includes positioning the tamper barrier no greater than approximately 0.06 mm from the first plurality of connection terminals.
14. The method of claim 1 wherein forming the tamper barrier includes positioning the tamper barrier no greater than approximately 0.05 to 0.06 mm from the first plurality of connection terminals.