IP Library Granted Patent US 7,135,924
Granted Patent B2
US 7,135,924 · App. 11/044,452 · Granted Nov 14, 2006

Cross-talk reduction circuit and method therefor

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Quick Facts
Patent No.
US 7,135,924
App. No.
11/044,452
Granted
Nov 14, 2006
Kind
B2
Abstract

In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.

Claims (30)

1. A cross-talk reduction circuit comprising:

a first differential pair having a first transistor coupled to a second transistor;

a second differential pair having a third transistor coupled to a fourth transistor;

a first feed-through transistor configured to receive a first input signal applied to the first transistor and responsively couple a representative first signal to the fourth transistor; and

a second feed-through transistor configured to receive a second input signal applied to the second transistor and responsively couple a representative second signal to the third transistor.

2. The cross-talk reduction circuit of claim 1 wherein a first current carrying electrode of the first transistor is coupled to a first current carrying electrode of the second feed-through transistor and to a first current carrying electrode of the third transistor.

3. The cross-talk reduction circuit of claim 2 wherein a first current carrying electrode of the second transistor is coupled to a first current carrying electrode of the first feed-through transistor and to a first current carrying electrode of the fourth transistor.

4. The cross-talk reduction circuit of claim 1 further including a third feed-through transistor configured to receive a third input signal applied to the third transistor and responsively couple a representative third signal to the second transistor.

5. The cross-talk reduction circuit of claim 4 further including a fourth feed-through transistor configured to receive a fourth input signal applied to the fourth transistor and responsively couple a representative fourth signal to the first transistor.

6. The cross-talk reduction circuit of claim 1 further including a first switch transistor configured to operably inhibit current flow through the first transistor and the second transistor when the first transistor receives the first input signal.

7. A method of forming a cross-talk reduction circuit comprising:

configuring a first differential pair to be selectively disabled;

coupling outputs of a second differential pair to outputs of the first differential pair; and

configuring the first differential pair to receive a first input signal and couple a representative first signal to an output of the second differential pair.

8. The method of claim 7 wherein coupling outputs of the second differential pair to outputs of the first differential pair includes coupling a first output of the first differential pair to a first output of the second differential pair and coupling a second output of the first differential pair to a second output of the second differential pair.

9. The method of claim 7 wherein configuring the first differential pair to receive the first input signal and couple the representative first signal to the output of the second differential pair includes coupling a first feed-through transistor to receive the first input signal and responsively couple the representative first signal to a first output of the second differential pair.

10. The method of claim 9 further including coupling a second feed-through transistor of the first differential pair to receive a second input signal and responsively couple a representative second signal to a second output of the second differential pair.

11. The method of claim 7 wherein configuring the first differential pair to receive the first input signal and couple the representative first signal to the output of the second differential pair includes configuring the first differential pair couple the representative first signal to an opposite output of the second differential pair when the first differential pair is disabled.

12. The method of claim 7 further including configuring the second differential pair to receive a second input signal and couple a representative second signal to an output of the first differential pair.

13. The method of claim 12 wherein configuring the second differential pair to receive the second input signal and couple the representative second signal to the output of the first differential pair includes coupling a first feed-through transistor of the second differential pair to receive the second input signal and responsively couple a representative first signal to a first output of the first differential pair.

14. The method of claim 12 wherein configuring the second differential pair to receive the second input signal and couple the representative second signal to the output of the first differential pair includes configuring the second differential pair to couple the representative second signal to an opposite output of the first differential pair when the first differential pair is disabled.

15. A method of reducing cross-talk comprising:

coupling outputs of a first differential pair to outputs of a second differential pair;

configuring the first differential pair to be disabled; and

configuring the first differential pair to receive a first input signal and responsively couple a first representative signal to an output of the second differential pair during at least a portion of a time that the first differential pair is disabled.

16. The method of claim 15 wherein configuring the first differential pair to receive the first input signal and responsively couple the first representative signal to the output of the second differential pair during at least the portion of the time that the first differential pair is disabled includes coupling a first output of the first differential pair to a first output of the second differential pair, coupling a second output of the first differential pair to a second output of the second differential pair, receiving the first input signal and responsively coupling the first representative signal to the second output of the second differential pair.

17. The method of claim 16 further including coupling a first feed-through transistor to receive the first input signal and responsively form the first representative signal.

18. The method of claim 17 further including coupling a control electrode of the first feed-through transistor to receive the first input signal, coupling a first current carrying electrode of the first feed-through transistor to the second output of the second differential pair, coupling a control electrode of a first input transistor of the first differential pair to receive the first input signal and coupling a first current carrying electrode of the first input transistor to the first output of the second differential pair.

19. The method of claim 18 further including coupling a control electrode of a second feed-through transistor to receive a second input signal, coupling a first current carrying electrode of the second feed-through transistor to the first output of the second differential pair, coupling a control electrode of a second input transistor of the first differential pair to receive the second input signal, and coupling a first current carrying electrode of the second input transistor to the second output of the second differential pair.

20. The method of claim 19 wherein configuring the first differential pair to be disabled includes coupling a switch transistor to a second current carrying electrode of the first input transistor and to a second current carrying electrode of the second input transistor.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →