Semiconductor device having reduced gate charge and reduced on resistance and method
View Patent ↗In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.
1. A semiconductor device comprising:
a semiconductor material having a first conductivity type and a first major surface;
first and second body regions of a second conductivity type disposed in the semiconductor material, wherein the first and second body regions are separated by a JFET region of the first conductivity type;
a first source region of the first conductivity type disposed in the first body region;
a gate layer comprising a conductive material disposed overlying the first major surface of the semiconductor material having a first opening over the JFET region and a second opening over the first body region, wherein the first opening is configured for reducing gate to drain capacitance; and
an interlevel dielectric layer disposed in the first opening over the semiconductor material.
2. The semiconductor device of claim 1 further comprising:
a first doped region of the first conductivity type disposed in the semiconductor material in the JFET region, wherein the first doped region has a higher doping concentration than the semiconductor material.
3. The semiconductor device of claim 2 wherein the first doped region has a dopant concentration of approximately 1.0×10 16 to 1.0×10 17 atoms/cm 3 .
4. The semiconductor device of claim 1 wherein the interlevel dielectric is comprised of silicon oxide.
5. The semiconductor device of claim 1 , wherein the gate layer is comprised of a refractory metal silicide.
6. The semiconductor device of claim 1 , wherein the semiconductor device comprises a vertical power MOSFET.
7. The semiconductor device of claim 1 , wherein the first opening is disposed over substantially all of the JFET region.
8. The semiconductor device of claim 1 , wherein the first opening is disposed over about 30 to 100 percent of the JFET region.
9. A vertical semiconductor device comprising:
a semiconductor material having a first conductivity type and a first major surface;
first and second body regions of a second conductivity type opposite the first conductivity type formed in the semiconductor material extending from the first major surface of the semiconductor material into a portion of semiconductor material, wherein a JFET region of the first conductivity type separates the first body region from the second body region;
a source region of first conductivity type formed in the first body region;
a gate dielectric layer overlying the JFET region and at least portions of the first and second body regions;
a gate layer comprising a conductive material formed overlying gate dielectric layer;
a first dielectric layer formed overlying the gate layer;
a first opening formed in the first dielectric layer and the gate layer over the JFET region;
a second opening formed in the first dielectric layer and the gate layer overlying the first body region; and
a second dielectric layer formed within the first opening for reducing gate to drain capacitance.
10. The device of claim 9 , wherein the second dielectric layer comprises a deposited oxide layer.
11. The device of claim 9 , wherein the second dielectric layer has a thickness from about 3,000 Angstroms to about 6,000 Angstroms.
12. The device of claim 9 further comprising a third dielectric overlying the second dielectric layer within the first opening.
13. The device of claim 12 , wherein the second dielectric layer comprises an oxide layer, and wherein the third dielectric layer comprises a nitride layer.
14. A vertical MOSFET device comprising:
a semiconductor material having a first conductivity type and a first major surface;
first and second body regions of a second conductivity type opposite the first conductivity type formed in the semiconductor material extending from the first major surface of the semiconductor material into a portion of semiconductor material, wherein the first and second body regions are spaced apart with a JFET region there between;
a first source region of the first conductivity type formed in the first body region;
a second source region of the first conductivity type formed in the second body region;
a conductive gate layer formed overlying the first major surface of the semiconductor material having a first opening overlying the JFET region configured to reduce gate charge, a second opening over the first body region, and a third opening over the second body region; and
a dielectric layer formed within the first opening.
15. The device of claim 14 further comprising a doped region of the first conductivity type formed in the JFET region, wherein the doped region has a higher doping concentration than the semiconductor material and is configured to reduce on-resistance.
16. The device of claim 14 , wherein the first and second body regions comprise a single body.
17. The device of claim 14 , wherein the first and second body regions comprise a cellular design.