IP Library Granted Patent US 7,733,116
Granted Patent B2
US 7,733,116 · App. 11/573,076 · Granted Jun 8, 2010

Method of testing a power supply controller and structure therefor

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Quick Facts
Patent No.
US 7,733,116
App. No.
11/573,076
Granted
Jun 8, 2010
Kind
B2
Abstract

A power supply controller ( 20 ) is configured to operate in a test mode that facilitates measuring the value of an output signal of an error amplifier ( 36 ) of the power supply controller ( 20 ).

Claims (14)

1. A method of forming a power supply controller comprising:

configuring the power supply controller for operation in a test mode for testing a control loop of the power supply controller and a normal mode for regulating a value of output voltage;

configuring the power supply controller to receive a feedback signal that is representative of the output voltage on a first input of an error amplifier and responsively form an output signal on an output of the error amplifier during the normal mode; and

configuring the power supply controller to operably couple a first signal that is representative of the output signal of the error amplifier to an input of the error amplifier during the test mode wherein the feedback signal is not coupled to the first input of the error amplifier.

2. The method of claim 1 further including configuring the power supply controller to receive a test mode signal and responsively operate in the test mode.

3. The method of claim 2 further including configuring the power supply controller to receive the test mode signal from a test pad internal to the power supply controller.

4. The method of claim 1 further including configuring the power supply controller to couple the output signal of the error amplifier to a terminal of the power supply controller.

5. The method of claim 1 further including measuring a value of the first signal.

6. The method of claim 5 further including adjusting a value of the first signal and again measuring the value of the first signal.

7. The method of claim 1 further including configuring the power supply controller to inhibit generating PWM drive signals during at least a portion of the test mode.

8. A method of forming a power supply controller comprising:

configuring the power supply controller for operation in a test mode and a normal mode for regulating a value of output voltage wherein the power supply controller generates PWM drive signals to regulate the value of the output voltage;

configuring the power supply controller to receive a feedback signal that is representative of the output voltage on a first input of an error amplifier and responsively form an output signal on an output of the error amplifier during the normal mode;

configuring the power supply controller to operably couple a first signal that is representative of the output signal of the error amplifier to an input of the error amplifier during the test mode including configuring the power supply controller to couple the output signal of the error amplifier to an input of an impedance translator and to couple an output signal of the impedance translator to the input of the error amplifier and to not couple the output signal of the error amplifier through the impedance translator to the input of the error amplifier in the normal mode.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: MIGLIAVACCA, PAOLO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038286/0398 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →