Method of forming an MOS transistor and structure therefor
View Patent ↗In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.
1. A method of forming an MOS transistor comprising:
providing a substrate having a first conductivity type and having a first surface;
forming a first doped region of a second conductivity type within at least a portion of the substrate and having a first peak doping concentration;
forming a second doped region of the first conductivity type overlying at least a portion of the first doped region and having a second peak doping that is no greater than the first peak doping concentration;
forming a third doped region of the first conductivity type overlying at least a portion of the second doped region and having a third peak doping concentration that is greater than the second peak doping concentration; and
forming an opening into the substrate with the opening having a sidewall juxtaposed to the first doped region and the second doped region.
2. The method of claim 1 further including forming a first insulator having a first thickness along at least a first portion of the sidewall juxtaposed to the first doped region, and forming a second insulator having a second thickness along at least a second portion of the sidewall juxtaposed to the second doped region wherein the second thickness is greater than the first thickness.
3. The method of claim 1 wherein forming the third doped region of the first conductivity type overlying at least the portion of the second doped region includes forming the third doped region spaced a first distance from the opening.
4. The method of claim 1 further including forming the MOS transistor having a first blocking junction that blocks voltage applied in a first direction across the MOS transistor and a second blocking junction that blocks voltages applied in a second direction across the MOS transistor.
5. The method of claim 1 wherein forming the second doped region includes forming the second peak doping concentration less than the first peak doping concentration.
6. The method of claim 5 further including forming the second peak doping concentration no greater than approximately 5E17 atoms/cm 3 .
7. The method of claim 5 wherein forming the third doped region includes forming the third peak doping concentration greater than the first peak doping concentration and the second peak doping concentration.
8. The method of claim 7 wherein forming the third doped region includes forming the third peak doping concentration no less than approximately 1E18 atoms/cm 3 .
9. A method of forming an MOS transistor comprising:
forming a channel region having a first conductivity type and having a first peak doping concentration;
forming a current carrying region of a second conductivity type overlying the channel region and having a second peak doping concentration that is no greater than the first peak doping concentration;
forming a first doped region overlying the current carrying region and having a third peak doping concentration; and
forming a trench gate structure having a first insulator of a first thickness juxtaposed to the channel region and having a second insulator of a greater thickness juxtaposed to a portion of the current carrying region.
10. The method of claim 9 wherein forming the trench gate structure includes forming the second insulator as a layer of a first dielectric along a sidewall of an opening within a semiconductor substrate and forming a second dielectric on the first dielectric.
11. The method of claim 9 wherein forming the trench gate structure includes forming a first dielectric along a sidewall of an opening within a semiconductor substrate and increasing a thickness of the first dielectric along a second portion of the sidewall that is juxtaposed to the current carrying region.
12. The method of claim 9 further including forming a first conductor of a first resistivity within the trench gate structure and adjacent to the first insulator, and forming a second conductor of a second resistivity within the first conductor wherein the second resistivity is less than the first resistivity.
13. The method of claim 9 wherein forming the current carrying region includes forming the second peak doping concentration of the current carrying region to have a lower doping concentration than the third peak doping concentration of the first doped region and the first peak doping concentration of the channel region.
14. A method of forming an MOS transistor comprising:
providing a semiconductor substrate of a first conductivity type having a first surface;
forming a channel region of a second conductivity type on the first surface;
forming a current carrying region of the first conductivity type overlying the channel region;
forming a trench gate structure extending from the first surface into the channel region and having a insulator of a first thickness juxtaposed to the channel region;
forming a first conductor within the trench gate structure adjacent to the insulator; and
forming a second conductor within the trench gate structure electrically connected to the first conductor wherein the second conductor has a lower resistivity than the first conductor.
15. The method of claim 14 wherein forming the first conductor includes forming a conductor comprising silicon.
16. The method of claim 14 wherein forming the second conductor includes forming a metal-silicon alloy.