IP Library Granted Patent US 7,820,473
Granted Patent B2
US 7,820,473 · App. 11/084,524 · Granted Oct 26, 2010

Schottky diode and method of manufacture

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Quick Facts
Patent No.
US 7,820,473
App. No.
11/084,524
Granted
Oct 26, 2010
Kind
B2
Abstract

A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A stacked structure is formed on a portion of the guard ring and a portion of the epitaxial layer. The stacked structure includes a layer of semi-insulating semiconductor material disposed on a layer of dielectric material. A first metal layer is formed on the portion of the epitaxial layer adjacent a first side of the stacked structure and on a first portion of the stacked structure. A second metal layer is formed on the portion of the epitaxial layer adjacent a second side of the stacked structure and on a second portion of the stacked structure.

Claims (46)

1. A method for manufacturing a Schottky diode having a breakdown voltage of at least about 250 volts, comprising:

providing a semiconductor material having a major surface, the semiconductor material of a first conductivity type;

forming a guard ring of a second conductivity type in the semiconductor material, wherein the guard ring extends from the major surface into the semiconductor material;

forming a first layer of dielectric material over a portion of the guard ring;

forming a layer of semi-insulating semiconductor material over a portion of the guard ring and on the first layer of dielectric material;

forming a second layer of dielectric material on the semi-insulating semiconductor material; and

forming an electrically conductive material on a portion of the major surface.

2. The method of claim 1 , further including removing the second layer of dielectric material after forming the electrically conductive material.

3. The method of claim 1 , wherein forming the electrically conductive material includes:

forming an etch mask over the second layer of dielectric material, wherein the etch mask has an opening that exposes a portion of the second layer of dielectric material;

removing a portion of the second layer of dielectric material; and

removing a portion of the semi-insulating semiconductor material exposed by removing the portion of the second layer of dielectric material to expose the portion of the major surface.

4. A method for manufacturing a Schottky diode having a breakdown voltage of at least about 250 volts, comprising:

providing a semiconductor material having a major surface, the semiconductor material of a first conductivity type;

forming a guard ring of a second conductivity type in the semiconductor material, wherein the guard ring extends from the major surface into the semiconductor material;

forming a layer of semi-insulating semiconductor material over a portion of the guard ring, wherein the layer of semi-insulating semiconductor material is one of semi-insulating polycrystalline silicon or alpha-silicon; and

forming an electrically conductive material on a portion of the major surface.

5. The method of claim 4 , wherein forming the electrically conductive material includes forming the electrically conductive material within the guard ring.

6. The method of claim 5 , wherein forming the electrically conductive material includes:

forming a metal silicide from the portion of the major surface; and

forming a metal layer on the metal silicide.

7. The method of claim 4 , wherein forming the guard ring in the semiconductor material includes doping the semiconductor material.

8. A method for manufacturing a Schottky diode having a reverse voltage of at least about 250 volts, comprising:

providing a semiconductor substrate having first and second major surfaces, the semiconductor substrate of a first conductivity type;

forming a layer of epitaxial material on the first major surface, the layer of epitaxial material of the first conductivity type;

forming a first layer of dielectric material on the layer of epitaxial material;

forming an opening in the first layer of dielectric material, the opening exposing a portion of the layer of epitaxial material;

forming a guard ring in the layer of epitaxial material, the guard ring of a second conductivity type and extending from the exposed portion of the layer of epitaxial material into the layer of epitaxial material;

forming a second layer of dielectric material on the exposed portion of the layer of epitaxial material;

forming a semi-insulating semiconductor material over a portion of the guard ring;

forming a third layer of dielectric material on the semi-insulating semiconductor material; and

forming an electrically conductive material over the layer of epitaxial material.

9. The method of claim 8 , further including forming an electrically conductive material on the second major surface.

10. The method of claim 8 , further including:

forming an etch mask on a first portion of the third layer of dielectric material;

etching a second portion of the third layer of dielectric material to expose a portion of the semi-insulating semiconductor material, the second portion unprotected by the etch mask;

etching the exposed portion of the semi-insulating semiconductor material to expose a portion of the first layer of dielectric material and a portion of the second layer of dielectric material; and

etching the exposed portions of the first and second layers of dielectric material to form a stacked structure having inner and outer sides and to expose a portion of the layer of epitaxial material within the stacked structure, a portion of the layer of epitaxial material adjacent the outer side of the stacked structure, and a portion of the guard ring.

11. The method of claim 10 , wherein forming the electrically conductive material on the layer of epitaxial material includes forming a layer of metal on the stacked structure, the portion of the layer of epitaxial material adjacent the outer side of the stacked structure, the exposed portion of the layer of epitaxial material within the stacked structure, and the exposed portion of the guard ring.

12. The method of claim 11 , wherein forming the layer of metal includes:

forming a refractory metal on the stacked structure, the portion of the layer of epitaxial material adjacent the outer side of the stacked structure, the exposed portion of the layer of epitaxial material within the stacked structure, and the exposed portion of the guard ring; and

forming a metal silicide from the portions of the refractory metal disposed on the layer of epitaxial material.

13. The method of claim 10 , further including:

removing the third layer of dielectric material after forming the metal silicide;

removing a portion of the electrically conductive material from a portion of the semi-insulating semiconductor material; and

removing a portion of the electrically conductive material adjacent to and spaced apart from the outer side of the annularly-shaped stacked structure.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2005
From: CHEN, LINGHUI; KRUSE, BLANCA ESTELA; DUSKIN, MARK; MORAN, JOHN D.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 016401/0063 →