IP Library Granted Patent US 7,737,004
Granted Patent B2
US 7,737,004 · App. 11/482,237 · Granted Jun 15, 2010

Multilayer gettering structure for semiconductor device and method

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Quick Facts
Patent No.
US 7,737,004
App. No.
11/482,237
Granted
Jun 15, 2010
Kind
B2
Abstract

In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

Claims (41)

1. A method of forming a semiconductor structure comprising the steps of:

providing a semiconductor substrate having a first major surface; and

forming a multi-layer structure overlying the first major surface comprising the steps of:

a. forming a polycrystalline semiconductor layer overlying the first major surface;

b. forming a dielectric layer overlying the first polycrystalline semiconductor layer; and

c. repeating steps a and b at least once; and

exposing the semiconductor substrate to an elevated temperature while using the multi-layer structure to getter unwanted impurities from within at least a portion of the semiconductor substrate.

2. The method of claim 1 further comprising the step of forming a first dielectric layer contacting the first major surface before forming any polycrystalline semiconductor layers.

3. The method of claim 1 , wherein the step of repeating steps a and b includes repeating steps a and b from one to twenty seven times.

4. The method of claim 1 , wherein the step of forming the polycrystalline semiconductor layer includes forming a polycrystalline silicon layer.

5. The method of claim 4 wherein the step of forming the polycrystalline silicon layer includes forming a polycrystalline silicon layer having a thickness in a range from about 0.01 microns to about 0.5 microns.

6. The method of claim 5 , wherein the step of forming the polycrystalline silicon layer includes forming a low pressure chemical vapor deposited polycrystalline silicon layer at a temperature in a range from about 550 degrees Celsius to about 750 degrees Celsius.

7. The method of claim 1 , wherein the step of forming the dielectric layer comprises forming an oxide layer.

8. The method of claim 7 , wherein the step of forming the oxide layer comprises forming a silicon dioxide layer having a thickness in a range from about 0.002 microns to about 0.05 microns.

9. A method of forming a semiconductor structure comprising the steps of:

providing a semiconductor substrate having a first major surface;

then in either order:

1. forming a polycrystalline semiconductor layer overlying the first major surface;

2. forming a dielectric layer overlying the first major surface; and

repeating steps 1 and 2 at least once; and

exposing the semiconductor substrate to a temperature sufficient to getter the semiconductor substrate.

10. The method of claim 9 wherein the step of forming the dielectric layer includes forming an oxide layer.

11. The method of claim 9 , wherein the step of forming the polycrystalline semiconductor layer includes forming a polysilicon layer.

12. The method of claim 9 further comprising the step of forming a semiconductor device on a second major surface of the semiconductor substrate opposite the first major surface.

13. A process for forming a semiconductor structure comprising the steps of:

providing a semiconductor substrate having a major surface;

forming a first pair of layers overlying the first major surface, wherein one layer comprises a polycrystalline semiconductor material and one layer comprises a dielectric material;

forming a second pair of layers overlying the first pair, wherein one layer comprises the polycrystalline semiconductor material and one layer comprises the dielectric material, wherein the first and second pairs form a multi-layer structure; and

using the multi-layer structure to getter the semiconductor substrate.

14. The process of claim 13 , wherein the step of forming the first pair of layers includes in either order:

forming a polysilicon layer overlying the major surface; and

forming an oxide layer overlying the major surface.

15. The process of claim 14 , wherein the step of forming the first pair of layers includes forming the first pair of layers in a low pressure chemical vapor deposition apparatus.

16. The process of claim 15 wherein the first pair of layers is formed in a single apparatus.

17. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a first major surface, a second major surface opposite the first major surface, and an extrinsic gettering structure formed overlying the first major surface, wherein the extrinsic gettering structure includes a multi-layer structure that comprises alternating layers of a polycrystalline semiconductor material and a dielectric material, and wherein the multi-layer structure comprises at least two pairs of alternating layers;

exposing the semiconductor substrate and the multi-layer structure to an elevated temperature, wherein the exposing step getters the semiconductor substrate; and

forming a semiconductor device in proximity to the second major surface.

18. The method of claim 17 , wherein the step of providing the semiconductor substrate includes providing the semiconductor substrate with an extrinsic gettering structure that comprises alternating layers of polysilicon and silicon oxide.

19. The method of claim 18 , wherein the step of providing the semiconductor substrate includes providing the semiconductor substrate with an extrinsic gettering structure that comprises from two to fourteen pairs.

20. The method of claim 17 , wherein the step of providing the semiconductor substrate includes providing the semiconductor substrate with an extrinsic gettering structure having a dielectric layer as a first layer adjacent the first major surface.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2006
From: LYSACEK, DAVID; LORENC, MICHAL; VALEK, LUKAS
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 018093/0123 →