Superjunction semiconductor device structure
View Patent ↗In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivity type semiconductor layers.
1. A superjunction switching device comprising:
a body of semiconductor material having a major surface;
a body region of a first conductivity type formed extending from the major surface into the body of semiconductor material;
a source region of a second conductivity type opposite the first conductivity type formed within the body region;
a control electrode formed in proximity to the body region and configured to form a channel region in the body region;
a charge compensation trench region formed in the body of semiconductor material, wherein the charge compensation trench region is configured to provide a current path for the superjunction switching device when in an on-state of operation, and wherein the charge compensation trench region is laterally set apart from the body region at the major surface so that the body of semiconductor material is interposed between the body region and the charge compensation trench region; and
a first conductive layer independent of the control electrode and electrically coupled to the charge compensation trench region, wherein the first conductive layer is configured to enhance switching speed when the superjunction switching device is switched from a first state to a second state.
2. The device of claim 1 wherein the body of semiconductor material includes a semiconductor substrate of the second conductivity type and an epitaxial layer formed overlying the semiconductor substrate.
3. The device of claim 2 wherein the epitaxial layer comprises the first conductivity type, and wherein the semiconductor substrate and the epitaxial layer form a primary blocking junction for the superjunction switching device.
4. The device of claim 3 further comprising:
a first doped region of the first conductivity type formed in the body of semiconductor material between the charge compensation trench region and the body region, wherein the first doped region has a higher dopant concentration than the epitaxial layer; and
a second doped region of the second conductivity type formed in the first doped region, wherein the second doped region is configured as a current path for the superjunction switching device.
5. The device of claim 1 further comprising:
a dielectric layer formed overlying the first conductive layer, wherein the dielectric layer has a sidewall surface;
a gate structure including the control electrode formed along the sidewall surface and adjacent the body and source regions and insulated from the first conductive layer.
6. The device of claim 5 further comprising a second conductive layer formed overlying the dielectric layer and coupled to the control electrode wherein the first conductive layer is between the body of semiconductor material and the second conductive layer, and wherein the dielectric layer and the first conductive layer are configured to reduce capacitance between the second conductive layer and the body of semiconductor material.
7. A semiconductor device comprising:
a body of semiconductor material having a major surface;
a body region of a first conductivity type formed extending from the major surface into the body of semiconductor material;
a charge compensation trench region formed in the body of semiconductor material, wherein the charge compensation trench region is configured to provide a current path for the semiconductor device when in an on-state of operation, and wherein the charge compensation trench region is laterally set apart from the body region at the major surface so that the body of semiconductor material is interposed between the body region and the charge compensation trench region;
a control electrode configured to switch the semiconductor device from a first state to a second state; and
a conductive ground plane layer formed overlying the body of semiconductor material and electrically coupled to the charge compensation trench region, wherein the conductive ground plane layer is insulated from the control electrode and configured to enhance switching speed of the semiconductor device.
8. The device of claim 1 , wherein the first conductive layer is further coupled to a conductive contact.
9. The device of claim 1 , further comprising a source contact layer electrically coupled to the source region, wherein the first conductive layer and the source contact layer are electrically connected.
10. The device of claim 1 , wherein the first conductive layer comprises a polycrystalline semiconductor material having the first conductivity type.
11. The device of claim 7 , wherein the body of semiconductor material includes a semiconductor substrate of the second conductivity type and an epitaxial layer formed overlying the semiconductor substrate.
12. The device of claim 11 wherein the epitaxial layer comprises the first conductivity type, and wherein the semiconductor substrate and the epitaxial layer form a primary blocking junction for the semiconductor device.
13. The device of claim 12 further comprising:
a first doped region of the first conductivity type formed in the body of semiconductor material between the charge compensation trench region and the body region, wherein the first doped region has a higher dopant concentration than the epitaxial layer; and
a second doped region of the second conductivity type formed in the first doped region, wherein the second doped region is configured as a current path for the semiconductor device.
14. The device of claim 7 further comprising a dielectric layer formed overlying the conductive ground plane layer, wherein the dielectric layer has a sidewall surface, and wherein the control electrode is formed along the sidewall surface.
15. The device of claim 14 further comprising a second conductive layer formed overlying the dielectric layer and coupled to the control electrode, wherein the conductive ground plane layer is between the body of semiconductor material and the second conductive layer, and wherein the dielectric layer and the first conductive layer are configured to reduce capacitance between the second conductive layer and the body of semiconductor material.
16. The device of claim 7 , wherein the conductive ground plane layer is further coupled to a conductive contact.
17. The device of claim 7 , further comprising:
a source region of the second conductivity type formed in the body region; and
a source contact layer electrically coupled to the source region, wherein the conductive ground plane layer and the source contact layer are electrically connected.
18. The device of claim 7 , wherein the conductive ground plane layer comprises a polycrystalline semiconductor material having the first conductivity type.