IP Library Granted Patent US 8,649,144
Granted Patent B2
US 8,649,144 · App. 11/671,034 · Granted Feb 11, 2014

Method of forming an over-voltage protection circuit and structure therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,649,144
App. No.
11/671,034
Granted
Feb 11, 2014
Kind
B2
Abstract

In one embodiment, an over-voltage protection circuit is configured to have two control circuits that respond at different values of the input voltage.

Claims (28)

1. An over-voltage protection circuit comprising:

an input configured to receive an input voltage;

an output;

a pass element transistor coupled between the input and the output and configured to couple the input voltage to the output;

a first circuit configured to disable the pass element transistor responsively to the input voltage being no less than a first value, the first circuit coupled to receive the input voltage and including a zener diode coupled to receive the input voltage, the first circuit including a resistor coupled in series with the zener diode and also including a another transistor coupled in parallel to the resistor wherein the first circuit is configured to enable the another transistor responsively to the input voltage being no less than the first value; and

a second circuit configured to disable the pass element transistor responsively to the input voltage being no less than a second value that is less than the first value, the second circuit coupled in parallel with the first circuit to receive the input voltage.

2. The over-voltage protection circuit of claim 1 wherein the second circuit includes a comparator configured to receive a sense signal that is representative of the input voltage and form a control signal used to disable the pass element transistor wherein the comparator is configured to form the control signal responsively to the input voltage being no less than second value.

3. The over-voltage protection circuit of claim 2 further including a feed forward circuit coupled to receive the input, voltage and form the sense signal.

4. The over-voltage protection circuit of claim 2 further including a first resistor coupled to enable the pass element transistor.

5. The over-voltage protection circuit of claim 1 further including a threshold shifting circuit coupled to the zener diode.

6. The over-voltage protection circuit of claim 1 further including a first transistor coupled to the zener diode and to a threshold shifting circuit and configured to form a control signal used to disable the pass element transistor responsively to the input voltage being no less than the first value.

7. The over-voltage protection circuit of claim 1 wherein an output of the first circuit is connected to an output of the second circuit.

8. The over-voltage protection circuit of claim 1 wherein the zener diode has an anode and a cathode, and further including a first transistor having a first current carrying electrode coupled to the pass element transistor, a control electrode coupled to the anode of the zener diode, and a second current carrying electrode coupled to a voltage return. of the over-voltage protection circuit.

9. The over-voltage protection circuit of claim 8 further including a first resistor having a first terminal coupled to the control electrode of the first transistor and a second terminal coupled to the voltage return, and also including a second resistor having a first terminal coupled to receive the input voltage and a second terminal coupled to the cathode of the zener diode.

10. The over-voltage protection circuit of claim 1 wherein the second circuit includes a comparator having a non-inverting input, an inverting input, and an output, and also including a first transistor having a control electrode coupled to the output of the comparator, a first current carrying electrode coupled to a voltage return of the over-voltage protection circuit, and a second current carrying electrode coupled to the pass element transistor.

11. The over-voltage protection circuit of claim 10 wherein the second circuit includes a feed-forward circuit coupled to receive the input voltage and couple a sense signal to the non-inverting input of the comparator wherein the sense signal is representative of the input voltage.

12. The over-voltage protection circuit of claim 1 wherein the first circuit including the zener diode is configured to disable the pass element transistor before the second circuit responsively to the input voltage being greater than the second value and no less than the first value for input voltage transitions having a rate that is greater than a first rate and where in the second circuit is configured to disable the pass element transistor before the first circuit responsively to the input voltage being no less than the second value for input voltage transitions having a rate that is less than the first rate.

13. A method of forming an over-voltage protection circuit comprising:

configuring a pass element of the over-voltage protection circuit to couple an input, voltage to an output of the over-voltage protection circuit;

coupling a first circuit of the over-voltage protection circuit to receive the input voltage and configuring the first circuit to decouple the input voltage from the output responsively to a first value of the input voltage for the input voltage increasing at a first rate;

coupling a second circuit of the over-voltage protection circuit in parallel with the first circuit to receive the input voltage and configuring the second circuit to decouple the input voltage from the output responsively to the input voltage increasing to no less than a second value at a second rate wherein the second value is greater than the first value; and

coupling an output of the first circuit and an output of the second circuit to a first transistor wherein both the first and second circuits disable the first transistor responsively to the input voltage having a value that is less than the first value and wherein disabling the first transistor causes the pass element to couple the input voltage to the output and also changes the second value to a third value that is less than the second value.

14. The method of claim 13 wherein configuring the second circuit of the over-voltage protection circuit includes configuring the second circuit to respond to the input voltage at a rate that is greater than the first circuit responds to the input voltage.

15. The method of claim 14 further including coupling a zener diode to receive the input voltage and to sense the input voltage increasing to the second value and responsively form a control signal that causes disabling the pass element.

16. The method of claim 15 further including coupling the zener diode to disable the pass element responsively to the second value.

17. The method of claim 13 wherein configuring the second circuit of the over-voltage protection circuit includes configuring the second rate to be greater than the first rate.

18. The method of claim 17 further including configuring a comparator of the first circuit to sense the first value after the second circuit senses the second value.

19. The method of claim 18 further including coupling a first input of the comparator to receive a sense signal that is representative of the input voltage, coupling a second input of the comparator to receive a reference signal, and coupling an output of the comparator to form a signal that causes disabling of the pass element.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2007
From: MIGLIAVACCA, PAOLO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 018851/0199 →