IP Library Granted Patent US 7,285,943
Granted Patent B2
US 7,285,943 · App. 10/512,767 · Granted Oct 23, 2007

Method of forming a reference voltage and structure therefor

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Quick Facts
Patent No.
US 7,285,943
App. No.
10/512,767
Granted
Oct 23, 2007
Kind
B2
Abstract

A selected bandgap reference ( 11 ) of a voltage generator ( 10 ) is operated at a duty cycle that is less than one hundred percent. The seclectable bandgap reference ( 11 ) has at a high current consumption when enabled and a low current consumption when disabled. The output voltage of the selectable bandgap reference ( 11 ) is stored on a storage element ( 13 ) when the selectable bandgap reference ( 11 ) is enabled. A high impedance amplifier ( 16 ) receives the stored voltage and generates the reference voltage.

Claims (27)

1. A method of forming a reference voltage generator comprising:

forming a bandgap circuit to be enabled to generate a reference voltage having a value during a first time period and to couple a storage device to the bandgap circuit and store the value of the reference voltage on the storage device responsively to the first time period;

forming the bandgap circuit to be disabled during a second time period; and

forming the reference voltage generator to decouple the storage device from receiving the reference voltage responsively to the second time period.

2. The method of claim 1 wherein forming the bandgap circuit to be enabled to generate the reference voltage having the value during the first time period includes forming the bandgap circuit to be operated at a duty cycle that is less than one hundred percent.

3. The method of claim 2 wherein forming the bandgap circuit to be operated at the duty cycle that is less than one hundred percent includes forming the band gap circuit to operate at the duty cycle that is less than fifty percent.

4. The method of claim 3 wherein forming the bandgap circuit to be operate at the duty cycle that is less than fifty percent includes forming the band gap circuit to operate at the duty cycle that is less than three percent.

5. The method of claim 1 wherein forming the bandgap circuit to be enabled to generate the reference voltage during the first time period includes forming the bandgap circuit to generate a second voltage having a value that is less than the value of the reference voltage during the second time period.

6. The method of claim 1 wherein forming the bandgap circuit to be enabled to generate the reference voltage having the value during the first time period includes forming the bandgap circuit to enable a selectable reference amplifier of the bandgap circuit during the first time period and to disable the selectable reference amplifier during the second time period.

7. The method of claim 1 including forming a storage device coupled to receive the wherein forming the reference voltage generator to decouple the storage device from receiving the reference voltage responsively to the second time period includes forming the reference voltage generator to retain the value on the storage device during the second time period.

8. The method of claim 7 further including forming an amplifier coupled to receive the value from the storage device during the first time period and the second time period.

9. The method of claim 1 wherein forming the bandgap circuit to be enabled to generate the reference voltage having the value during the first time period includes forming a timing circuit to generate a pulse having a duty cycle.

10. A method of generating a reference voltage comprising:

coupling a bandgap reference circuit to receive operating current and to responsively generate a reference voltage having a first value during a first interval of an operating cycle of the bandgap reference circuit, and decoupling the bandgap reference circuit from receiving the operating current and responsively inhibit generating the first value during a second interval of the operating cycle wherein the first interval of the operating cycle is less than one hundred percent.

11. The method of claim 10 wherein decoupling the bandgap reference circuit from receiving the operating current and responsively inhibit generating the first value includes coupling the bandgap reference circuit to generate a second value that is less than the first value responsively to the second interval.

12. The method of claim 10 further including coupling the bandgap reference circuit to a storage element responsively to the first interval and storing the first value on the storage element, and decoupling the storage element from the bandgap reference circuit and retaining the first value on the storage responsively to the second interval.

13. The method of claim 12 further including coupling the storage element to an amplifier having a high input impedance.

14. The method of claim 10 wherein coupling the bandgap reference circuit to receive the operating current and to responsively generate the reference includes enabling a selectable reference amplifier during the first interval wherein the selectable reference amplifier provides the operating current to the bandgap reference circuit, and disabling the selectable reference amplifier after the first interval expires.

15. The method of claim 10 further including configuring a timing circuit to form a timing signal having an asymmetrical waveform and using the timing signal for coupling the bandgap reference circuit to receive the operating current.

16. A reference voltage device comprising:

a selectable reference amplifier having an output, a first input, and a second input;

a first reference transistor having a first current carrying electrode coupled to receive current from the selectable reference amplifier through a first and second series connected resistors wherein the second series connected resistor is coupled to supply a voltage to the first input of the selectable reference amplifier;

a second reference transistor having a first current carrying electrode coupled to receive current from the selectable reference amplifier through a third series connected resistor wherein the third series connected resistor is coupled to supply a voltage to the second input of the selectable reference amplifier; and

a timing circuit coupled to provide a timing signal to selectively enable and disable the selectable reference amplifier.

17. The reference voltage device of claim 16 further including a comparator coupled to receive an output voltage from the output of the selectable reference amplifier and an internal voltage from the first current carrying electrode of the second reference transistor and to responsively generate a control signal representative of a difference between the output voltage and the internal voltage.

18. The reference voltage device of claim 17 further including a transistor coupled to receive the output voltage and to transfer the output voltage to a storage element responsively to the control signal.

19. The reference voltage device of claim 16 wherein the first reference transistor and the second reference transistor are transistors within a bandgap reference circuit.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →