Power system inhibit method and device and structure therefor

1. A high voltage multiple output current device comprising:

a substrate of a first conductivity type;

a first doped region of a second conductivity type on a first portion of the substrate, the first doped region formed as a first closed geometric shape having a center and a first periphery wherein a first portion of the first periphery has a first contour and a second portion of the first periphery has a second contour and also wherein the first doped region is a drain and a source of a J-FET transistor, a drain of a first MOS transistor, and a drain of a second MOS transistor;

a second doped region of the second conductivity type on the substrate and having a second periphery wherein a portion of the second periphery is juxtaposed to the first portion of the first periphery and has a third contour that is the same shape as the first contour wherein the second doped region is a source of the first MOS transistor; and

a third doped region of the second conductivity type on the substrate and having a third periphery wherein a portion of the third periphery is juxtaposed to the second portion of the first periphery and has a fourth contour that is the same shape as the second contour, and wherein the third doped region is a source of the second MOS transistor.

2. The high voltage multiple output current device of claim 1 further including a first gate structure overlying a portion of the first portion of the first periphery and the second periphery, and also including a second gate structure overlying a portion of the second portion of the first periphery and the third periphery.

3. The high voltage multiple output current device of claim 1 further including a fourth doped region of the second conductivity type within the first doped region, the fourth doped region having a heavier doping than the first doped region.

4. The high voltage multiple output current device of claim 1 further including a low on resistance transistor coupled to receive current from the first MOS transistor and responsively conduct an ESD to a voltage return.

5. The high voltage multiple output current device of claim 4 wherein the low on-resistance transistor is also coupled to the drain of the J-FET transistor.

6. The high voltage multiple output current device of claim 4 further including an operating voltage detector having an input coupled to receive an output voltage of the second MOS transistor and to disable the second MOS transistor when the output voltage is equal to or greater than a desired value.

7. The high voltage multiple output current device of claim 4 further including a first current control loop coupled to receive current from the third doped region of the second conductivity type, the first current control loop having an output; a second current control loop coupled to receive current from the second doped region of the second conductivity type, the second current control loop having an output; and a capacitor coupled to the output of the first and second current control loops.

8. The high voltage multiple output current device of claim 7 further including an operating voltage detector having an input coupled to the output of the first current control loop to receive an output voltage of the first and second current control loops and to disable the first MOS transistor and the second MOS transistor when the output voltage is equal to or greater than a desired value.

9. The high voltage multiple output current device of claim 8 further including an inhibit transistor coupled to the output of the first current control loop to couple current from the second MOS transistor to a voltage return.

10. A high voltage multiple output current device comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type on a first portion of the substrate, the first region having a shape and a first periphery wherein a first portion of the first periphery has a first contour and a second portion of the first periphery has a second contour and also wherein the first region is a drain and a source of a JFET transistor, a drain of a first MOS transistor, and a drain of a second MOS transistor;

a second region of the second conductivity type on the substrate and having a second periphery wherein a portion of the second periphery is juxtaposed to the first portion of the first periphery and has a third contour that is the same shape as the first contour wherein the second region is a source of the first MOS transistor; and

a third region of the second conductivity type on the substrate and having a third periphery wherein a portion of the third periphery is juxtaposed to the second portion of the first periphery and has a fourth contour that is the same shape as the second contour, and wherein the third region is a source of the second MOS transistor.

11. The high voltage multiple output current device of claim 10 further including a first gate structure overlying a portion of the first portion of the first periphery and the second periphery, and also including a second gate structure overlying a portion of the second portion of the first periphery and the third periphery.

12. The high voltage multiple output current device of claim 10 further including a fourth region of the second conductivity type within the first region, the 35 fourth region having a heavier doping than the first region.

13. The device of claim 10 wherein the shape of the first region is one of a circle, an ellipse, a square, a rectangle, a pentagon, or a hexagon and wherein the first portion of the first periphery is a first distance from a center of the shape of the first region.

14. The device of claim 13 wherein the portion of the periphery of the second region has a second distance from the center of the shape of the first region and wherein the portion of the periphery of the third region has a third distance from the center of the shape of the first region.