Delay circuit and method therefor

1. A delay circuit comprising:

first and second differential transistors coupled as a differential pair;

a first cascode transistor coupled to receive a signal from the first differential transistor, the first cascode transistor having a first current carrying electrode, a second current carrying electrode, and a control electrode;

a second cascode transistor coupled to receive a signal from the second differential transistor, the second cascode transistor having a first current carrying electrode coupled to the control electrode of the first cascode transistor, a control electrode coupled to the first current carrying electrode of the first cascode transistor, and a second current carrying electrode

a first emitter follower transistor coupled to receive a signal from the first cascode transistor, the first emitter follower transistor having a first current carrying electrode and a second current carrying electrode; and

a second emitter follower transistor coupled to receive a signal from the second cascode transistor, the second emitter follower transistor having a first current carrying electrode and a second current carrying electrode.

2. The delay circuit of claim 1 wherein the first emitter follower transistor includes the first emitter follower transistor having a base coupled to the first current carrying electrode of the first cascode transistor, and an emitter coupled to a first output of the delay circuit.

3. The delay circuit of claim 2 wherein the first cascade transistor includes the second current carrying electrode of the first cascode transistor coupled to the first current carrying electrode of the first differential transistor.

4. The delay circuit of claim 3 further including the second current carrying electrode of the first differential transistor is coupled to the first current carrying electrode of the second differential transistor.

5. The delay circuit of claim 2 wherein the second emitter follower transistor includes the second emitter follower transistor having a base coupled to the first current carrying electrode of the second cascode transistor, and an emitter coupled to a second output of the delay circuit.

6. The delay circuit of claim 5 wherein the second cascode transistor includes the second current carrying electrode of the second cascode transistor coupled to the first current carrying electrode of the second differential transistor.

7. The delay circuit of claim 1 further including a first load resistor coupled between the first cascode transistor and a power input of the delay circuit.

8. The delay circuit of claim 7 further including a second load resistor coupled between the second cascode transistor and the power input of the delay circuit.

9. A method of forming a delay circuit comprising:

forming a differential pair coupled to receive input signals;

configuring cascode coupled transistors to receive signals from the differential pair; and

configuring follower coupled transistors to receive signals from the cascode coupled transistors and form output signals representative of the input signals and delayed from the input signals including coupling a control electrode of a first follower transistor to a first current carrying electrode of a first cascode transistor, coupling a first current carrying electrode of the first follower transistor to a first output of the delay circuit, coupling a control electrode of a second follower transistor to a first current carrying electrode of a second cascode transistor, and coupling a first current carrying electrode of the second follower transistor to a second output of the delay circuit; and

coupling a first bias transistor to the first current carrying electrode of the first follower transistor and coupling a second bias transistor to the first current carrying electrode of the second follower transistor.

10. The method of claim 9 wherein configuring cascode coupled transistors to receive signals from the differential pair includes coupling the cascode coupled transistors in series between the differential pair and a power input to the delay circuit.

11. The method of claim 9 wherein configuring follower coupled transistors to receive signals from the cascode coupled transistors includes coupling The emitter follower coupled transistors to collectors of the cascode coupled transistors.

12. The method of claim 9 further including coupling a second current carrying electrode of the first cascode transistor to a first current carrying electrode of a first differential transistor of the differential pair and coupling a second current carrying electrode of the second cascode transistor to a first current carrying electrode of a second differential transistor of the differential pair.

13. The method of claim 12 further including coupling a second current carrying electrode of the first differential transistor to a second current carrying electrode of the second differential transistor.

14. The method of claim 13 further including coupling a bias circuit to the second current carrying electrode of the first differential transistor and to the second current carrying electrode of the second differential transistor.

15. The method of claim 9 further including coupling a control electrode of the first cascode transistor to the first current carrying electrode of the second cascode transistor and coupling a control electrode of the second cascode transistor to the first current carrying electrode of the second cascode transistor.

16. A method of forming a delay circuit comprising:

forming a differential pair coupled to receive input signals;

configuring cascode coupled transistors to receive signals from the differential pair;

configuring follower coupled transistors to receive signals from the cascode coupled transistors and form output signals representative of the input signals and delayed from the input signals; and

coupling a bias circuit in series with the differential pair to control current through the differential pair wherein the bias circuit is devoid of another differential pair.