Method of forming a low capacitance semiconductor device and structure therefor
View Patent ↗In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
1. A semiconductor device comprising:
a substrate of a first conductivity type having a first surface;
a first source region of the first conductivity type on the first surface of the substrate;
a second source region of the first conductivity type on the first surface of the substrate wherein the second source region is spaced apart from the first source region;
a gate structure overlying the first surface of the substrate, the gate structure having a first end overlying an edge of the first source region, a second end overlying an edge of the second source region, the gate structure having a first surface substantially parallel to the first surface of the substrate and facing away from the first surface of the substrate;
an opening extending from the first surface of the gate structure into the gate structure including the opening having sidewalls;
an insulator on at least sidewalls of the opening; and
a conductor abutting the insulator and within the opening wherein the conductor does not overlie the first region or the second source region.
2. The semiconductor device of claim 1 wherein the conductor is doped polysilicon.
3. The semiconductor device of claim 1 further including a first body region of a second conductivity type on the first surface of the substrate with the first source region disposed within the first body region; and
a second body region of the second conductivity type on the first surface of the substrate with the second source region within the second body region wherein the second body region is spaced apart from the first body region.
4. The semiconductor device of claim 3 wherein the conductor substantially does not extend onto the first surface of the gate structure.
5. A semiconductor device comprising:
a substrate of a first conductivity type having a first surface;
a first source region of the first conductivity type on the first surface of the substrate;
a second source region of the first conductivity type on the first surface of the substrate wherein the second source region is spaced apart from the first source region;
a gate structure overlying the first surface of the substrate, the gate structure having a first end overlying an edge of the first source region, a second end overlying an edge of the second source region, the gate structure having a first surface substantially parallel to the first surface of the substrate and facing away from the first surface of the substrate;
a gate conductor of the gate structure overlying the substrate;
an insulator layer of the gate structure on the gate conductor;
a first conductor on the insulator layer; and
a source conductor on the first conductor.
6. The semiconductor device of claim 5 wherein the insulator layer is no thicker than about 10,000 Angstroms.