Encapsulated electronic device structure
View Patent ↗In one embodiment, an electronic device package ( 1 ) includes a leadframe ( 2 ) with a flag ( 3 ). An electronic chip ( 8 ) is attached to the flag ( 3 ) with a die attach layer ( 9 ). A trench ( 16 ) having curved sidewalls is formed in the flag ( 3 ) in proximity to the electronic chip ( 8 ) and surrounds the periphery of the chip ( 8 ). An encapsulating layer ( 19 ) covers the chip ( 8 ), portions of the flag ( 3 ), and at least a portion of the curved trench ( 16 ). The curved trench ( 16 ) reduces the spread of die attach material across the flag ( 3 ) during chip attachment, which reduces chip and package cracking problems, and improves the adhesion of encapsulating layer ( 19 ). The shape of the curved trench ( 16 ) prevents flow of die attach material into the curved trench ( 16 ), which allows the encapsulating layer ( 19 ) to adhere to the surface of the curved trench ( 16 ).
1. An electronic device package comprising:
a support substrate including a flag, wherein the flag has a bonding surface;
a first electronic chip having a first peripheral edge, wherein the first electronic chip is attached to a first portion of the bonding surface with a first die attach material;
a first continuous trench for restricting flow of the first die attach material on the bonding surface, wherein the first continuous trench is formed in the flag in proximity to the first peripheral edge and extending only partially into the flag, wherein the first continuous trench includes a continuously rounded cross-sectional shape, a curved sidewall surface, and an inner edge substantially aligned to the first peripheral edge, and wherein the first continuous trench surrounds the first electronic chip, and wherein the first die attach material terminates at approximately the inner edge; and
an encapsulant covering the first electronic chip and at least a portion of the curved sidewall surface.
2. The package of claim 1 , wherein the first continuous trench has a width between about one hundred two microns and about three hundred thirty microns.
3. The package of claim 1 , wherein the first continuous trench has a cross-sectional shape comprising an inverse omega shape.
4. The package of claim 1 , wherein the first continuous trench has a rounded corner.
5. The package of claim 1 , wherein the first continuous trench has depth in range from about 100 microns to about 330 microns.
6. A leadless electronic structure comprising:
a leadframe including a bonding site and a flag having a bonding surface;
a first semiconductor device having a first peripheral edge coupled to the bonding surface with a first chip attach layer, wherein the first semiconductor device includes a bond pad;
a first groove for controlling flow of the first chip attach layer, wherein the first groove is formed in the bonding surface surrounding the first semiconductor device and extending only partially into the flag, wherein the first groove comprises a substantially continuously curved inner surface and a first inner edge at the bonding surface substantially aligned with the first peripheral edge, and wherein at least a portion of first chip attach layer extends across the bonding surface and terminates at approximately the first inner edge;
a bonding device coupling the bond pad to the bonding since; and
an encapsulating layer covering portions of the flag, the bonding site, and the bonding device, the first semiconductor device, and at least a portion of the substantially continuously curved inner surface.