IP Library Granted Patent US 7,736,984
Granted Patent B2
US 7,736,984 · App. 11/232,757 · Granted Jun 15, 2010

Method of forming a low resistance semiconductor contact and structure therefor

Assignee: Semiconductor Components Industries, LLC
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Quick Facts
Patent No.
US 7,736,984
App. No.
11/232,757
Granted
Jun 15, 2010
Kind
B2
Abstract

In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.

Claims (36)

1. A method of forming a semiconductor contact comprising:

providing a semiconductor substrate having a first surface;

forming a first doped region of a first conductivity type within the semiconductor substrate;

forming a second doped region of a second conductivity type on the first surface and adjoining the first doped region;

forming a first silicide on a portion of the second doped region and electrically contacting the second doped region on the first surface including using a first metal that forms a low resistance electrical connection to the second doped region to form the first silicide;

forming a second silicide on a portion of the first doped region including using a second metal that forms a low resistance electrical connection to the second doped region to form the second silicide wherein the second metal is different from the first metal; and

forming a conductor material electrically contacting both the first silicide and the second silicide.

2. The method of claim 1 wherein forming the second doped region includes forming the second doped region overlying the portion of the first doped region.

3. The method of claim 2 wherein forming the second silicide on the portion of the first doped region includes forming an opening through the second doped region and exposing the portion of the first doped region prior to forming the second silicide.

4. The method of claim 2 wherein forming the second doped region of the second conductivity type on the first surface and adjoining the first doped region includes doping a first portion of the semiconductor substrate with the first conductivity type to form the first doped region and doping the first doped region with the second conductivity type to form the second doped region on the surface of the semiconductor substrate.

5. The method of claim 1 further including forming the first silicide and the second silicide through one contact opening.

6. The method of claim 1 wherein forming the second doped region of the second conductivity type on the first surface and adjoining the first doped region includes doping a first portion of the first surface to form the first doped region and doping a second portion of the first surface adjacent to the first portion to form the second doped region.

7. The method of claim 1 wherein forming the first silicide electrically contacting the second doped region includes protecting the first doped region and forming the first silicide and subsequently forming the second silicide on the portion of the first doped region.

8. The method of claim 1 wherein forming the second silicide on the portion of the first doped region includes forming a recess in the first doped region adjacent the second doped region and subsequently forming the second silicide along the recess.

9. The method of claim 1 further including forming the second conductivity type to be opposite to the first conductivity type.

10. The method of claim 1 further including forming the conductor material to physically contact both the first and second silicides.

11. A method of forming a semiconductor contact comprising:

providing a semiconductor substrate having a first surface;

forming a first doped region of a first conductivity type within the semiconductor substrate;

forming a second doped region of a second conductivity type on the first surface and adjoining the first doped region;

forming a first silicide electrically contacting the second doped region on the first surface;

forming a protective spacer overlying the first silicide and exposing a portion of the second doped region overlying the portion of the first doped region, and forming an opening through the portion of the second doped region and exposing the portion of the first doped region wherein the second doped region overlies the portion of the first doped region;

forming a second silicide on the portion of the first doped region; and

forming a conductor material electrically contacting both the first silicide and the second silicide.

12. The method of claim 11 wherein forming the first silicide electrically contacting the second doped region includes forming the first silicide on the portion of the second doped region overlying the portion of the first doped region and on another portion of the second doped region not overlying the portion of the first doped region, and forming the protective spacer on the first silicide.

13. A method of forming a semiconductor contact comprising:

providing a semiconductor substrate having a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region;

forming a first metal silicide between the first doped region and a first metal wherein the first metal silicide physically contacts and is electrically contacting a portion of the first doped region;

forming a second metal silicide between the second doped region and a second metal wherein the second metal silicide physically contacts and is electrically contacting the second doped region and wherein the first metal is different from the second metal; and

forming a conductor electrically contacting the first metal silicide and the second metal silicide.

14. The method of claim 13 wherein forming the first metal silicide includes forming the first metal silicide and the second metal silicide a through single contact opening.

15. The method of claim 14 wherein providing the semiconductor substrate includes providing the first doped region overlapping a portion of the second doped region.

16. The method of claim 13 wherein providing the semiconductor substrate includes providing the first doped region extending further into the semiconductor substrate than the second doped region.

17. The method of claim 13 further including forming the second conductivity type to be opposite to the first conductivity type.

18. The method of claim 13 further including forming the first metal silicide using a metal that forms a low resistance electrical connection between the first doped region and the first metal; and

forming the first metal silicide using another metal that forms a low resistance electrical connection between the second doped region and the second metal.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2005
From: GRIVNA, GORDON M.; VENKATRAMAN, PRASAD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 017031/0022 →
Continuity (1)
Related Publication 20070072416A1 · Mar 29, 2007