IP Library Granted Patent US 8,168,466
Granted Patent B2
US 8,168,466 · App. 11/757,222 · Granted May 1, 2012

Schottky diode and method therefor

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Quick Facts
Patent No.
US 8,168,466
App. No.
11/757,222
Granted
May 1, 2012
Kind
B2
Abstract

In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Claims (35)

1. A method of forming a Schottky diode comprising:

forming a first region of a first conductivity type having a first doping concentration on a semiconductor substrate;

forming a Schottky junction overlying a portion of the first region;

forming a guard ring on the semiconductor substrate and surrounding an outside edge of the Schottky junction;

forming an MOS gate overlying a surface of the semiconductor substrate and positioned between the guard ring and a portion of a field oxide region and

forming a second doped region of the first conductivity type having a third doping concentration overlapping the first region and spaced a first distance from the first doped region, wherein the third doping concentration is greater than the first doping concentration.

2. The method of claim 1 further including forming a second doped region of the first conductivity type having a third doping concentration overlapping the first region and spaced a first distance from the first doped region, wherein the third doping concentration is greater than the first doping concentration.

3. A method of forming a Schottky diode comprising:

forming a first region of a first conductivity type having a first doping concentration on a semiconductor substrate;

forming a Schottky junction overlying a portion of the first region;

forming a guard ring on the semiconductor substrate and surrounding an outside edge of the Schottky junction;

forming an MOS gate overlying a surface of the semiconductor substrate and positioned between the guard ring and a portion of a field oxide region;

forming a first doped region of the first conductivity type having a second doping concentration overlapping the first region including forming a conductor on the first doped region to form the Schottky junction wherein the second doping concentration is greater than the first doping concentration;

forming a second doped region of the first conductivity type having a third doping concentration overlapping the first region and spaced a first distance from the first doped region, wherein the third doping concentration is greater than the first doping concentration;

forming a third doped region of the first conductivity type within the second doped region and forming another conductor on the third doped region to form electrical contact thereto; and

forming a fourth doped region of a second conductivity type having a fourth doping concentration within the second doped region and spaced a first distance from the third doped region.

4. The method of claim 2 wherein forming the first and second doped regions overlapping the first region includes forming the first region as a doped portion of the semiconductor substrate wherein the semiconductor substrate has a second conductivity type.

5. The method of claim 1 wherein forming the guard ring on the semiconductor substrate includes forming a first doped region of a second conductivity type on the semiconductor substrate and surrounding the outside edge of the Schottky junction.

6. A method of forming a Schottky diode comprising:

providing a substrate of a first conductivity type having a first doping concentration;

forming a first doped region of a second conductivity type having a second doping concentration on a surface of the substrate;

forming a second doped region of the second conductivity type having a third doping concentration that is greater than the second doping concentration overlapping the first doped region;

forming a Schottky junction overlying a portion of the first doped region and spaced apart from the second doped region; and

forming a third doped region of the first conductivity type having a fourth doping concentration that is greater than the second doping concentration within the second doped region and spaced a first distance from the Schottky junction.

7. The method of claim 6 further including forming a fourth doped region of the second conductivity type having a fifth doping concentration overlapping the first doped region including forming a conductor on the first doped region to form the Schottky junction wherein the fifth doping concentration is greater than the second doping concentration.

8. The method of claim 7 further including a fifth doped region of the first conductivity type extending into the fourth doped region and surrounding the Schottky junction.

9. The method of claim 7 further including forming first and second field oxide regions on the substrate wherein the first field oxide region overlies a portion of the first doped region and wherein a portion of the second field oxide region overlies a portion of the fourth doped region; and forming an MOS gate surrounding the Schottky junction wherein the MOS gate is positioned between the Schottky junction and the first and second field oxide regions.

10. The method of claim 6 further including forming a fourth doped region of the second conductivity type within the second doped region and forming a conductor on the fourth doped region to form electrical contact thereto wherein the fourth doped region is spaced a second distance from the third doped region.

11. The method of claim 6 further including forming an MOS transistor on the substrate with the Schottky diode and spaced apart from the Schottky diode.

12. The method of claim 1 wherein forming the MOS gate includes forming the MOS gate overlying a portion of the guard ring.

13. The method of claim 12 further including forming a thin insulator of the MOS gate overlying an edge of the guard ring.

14. The method of claim 13 wherein the thin insulator extends from the field oxide region to overlie the edge of the guard ring.

15. The method of claim 6 wherein forming the Schottky junction overlying the portion of first doped region includes forming the Schottky junction spaced laterally apart from the second doped region.

16. The method of claim 6 further including forming a fourth doped region within the first doped region and underlying the Schottky junction.

17. The method of claim 16 further including forming the fourth doped region spaced laterally apart from the second doped region.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2009
From: HOSSAIN, ZIA
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 023481/0495 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2007
From: QUDDUS, MOHAMMED TANVIR; TU, SHANGHUI L.; ROZSYPAL, ANTONIN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 019371/0282 →