Filter having integrated floating capacitor and transient voltage suppression structure and method of manufacture
View Patent ↗In one embodiment, a filter structure that integrates one plate of a capacitor with an electrode of a transient voltage device. The filter structure includes a well region of one conductivity type formed in semiconductor substrate of an opposite conductivity type. The well region forms one plate of the capacitor and an electrode of the transient voltage suppression device. A dielectric layer is formed over a portion of the well region and a conductive layer is formed overlying the dielectric layer to provide a second plate of the capacitor. The dopant concentration of the well region provides a constant capacitance/voltage characteristic for the filter structure when a selected voltage range is applied to plates of the capacitor.
1. A semiconductor filter structure comprising:
a semiconductor substrate of a first conductivity type and having a first major surface and a second major surface opposite to the first major surface;
a first doped region of a second conductivity type formed in the semiconductor substrate;
a first dielectric layer formed overlying a portion of the first doped region, wherein the first doped region is continuous adjacent to the first dielectric layer;
a second doped region of the second conductivity type formed in the semiconductor substrate;
a second dielectric layer formed overlying a portion of the second doped region, wherein the second doped region is continuous adjacent to the second dielectric layer;
a third doped region of the second conductivity type formed in the semiconductor substrate;
a third dielectric layer formed overlying a portion of the third doped region, wherein the third doped region is continuous adjacent to the third dielectric layer;
a first conductive electrode formed overlying the semiconductor substrate and coupled to the first doped region;
a second conductive electrode formed overlying the first dielectric layer and overlying the second dielectric layer; and
a third conductive electrode formed overlying the third dielectric layer and coupled to the second doped region, wherein the first doped region forms a first plate of a first capacitor and a first electrode of a first TVS device, and wherein the second doped region forms a first plate of a second capacitor and a first electrode of a second TVS device, and wherein the third doped region forms a first plate of a third capacitor and a first electrode of a third TVS device, and wherein the second major surface forms a second electrode for at least one of the first, second and third TVS devices.
2. The structure of claim 1 , wherein the semiconductor substrate has a dopant concentration of about 1.0×10 19 atoms/cm 3 .
3. The structure of claim 2 , wherein the first, second, and third doped regions have dopant concentrations of about 1.0×10 20 atoms/cm 3 .
4. The filter structure of claim 1 further comprising a first multilayer inductor overlying at least a portion of the semiconductor substrate, the first multilayer inductor having a first terminal and a second terminal, the first multilayer inductor also having a first conductor overlying the portion of the semiconductor substrate, a second conductor overlying at least a portion of the first conductor a first dielectric disposed between the first conductor and the second conductor, wherein the first terminal is coupled to the first conductive electrode and second terminal is coupled to the second conductive electrode.
5. The filter structure of claim 4 wherein the first conductor and the second conductor are metal conductors.
6. The filter structure of claim 4 further including a second multilayer inductor coupled to the first multilayer inductor and having a first terminal and a second terminal, wherein the first terminal of the second multilayer inductor is coupled to the third conductive electrode, and wherein the second terminal of the second multilayer inductor is coupled to the second conductive electrode.