Semiconductor structure with improved on resistance and breakdown voltage performance
View Patent ↗A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.
1. A lateral IGFET device comprising:
a semiconductor substrate;
a first region of a first conductivity type formed as part of the semiconductor substrate, wherein the semiconductor substrate and the first region are in physical contact without an intervening insulating layer between them;
a body region of a second conductivity type formed in the semiconductor substrate adjacent the first region;
a source region of the first conductivity type formed in the body region;
a drain contact region of the first conductivity type formed in the first region to provide a lateral IGFET device configuration;
a gate structure formed adjacent to the body region; and
a super junction structure formed in the first region and laterally spaced apart from the body region so that a portion of the first region is between the super junction structure and the body region, the super junction structure including a pair of spaced apart filled striped trenches, a first striped doped region of the first conductivity type and a second striped doped region of the second conductivity type between the pair of spaced apart filled striped trenches, wherein the first striped doped region has a higher doping concentration than the first region, and wherein the pair of spaced apart filled striped trenches terminate within the first region thereby leaving another portion of the first region between lower surfaces of the pair of spaced apart filled striped trenches and the substrate, and wherein the first and second striped doped regions do not wrap entirely around the lower surfaces of the pair of spaced apart filled striped trenches.
2. The device of claim 1 wherein the pair of spaced apart filled striped trenches and the first and second striped doped region terminate at a depth in the first region that is substantially equal.
3. The device of claim 1 wherein the pair of spaced apart filled striped trenches comprises trenches filled with a dielectric material extending to a major surface of the semiconductor substrate.
4. The device of claim 1 further comprising a third striped doped region of the first conductivity type between the pair of spaced apart filled striped trenches.
5. The device of claim 1 further comprising a third striped doped region of the second conductivity type between the pair of spaced apart filled striped trenches.
6. The device of claim 1 , wherein the gate structure comprises a planar gate structure, the device further comprising a trench gate structure formed adjacent the body region.
7. The device of claim 1 , wherein the super junction structure consists of the first doped striped region formed adjoining one of the pair striped filled trenches and the second doped striped region formed adjoining another of the pair of striped filled trenches, and wherein first doped striped region adjoins the second doped striped region.
8. The device of claim 1 further comprising an insulating layer formed in the semiconductor substrate adjacent lower surfaces of the pair of filled striped trenches, wherein the insulating layer is confined within first region so that the insulating layer does not underlie the body region.
9. The device of claim 1 , wherein the pair of striped filled trenches are formed with a dielectric material and SIPOS.
10. The device of claim 1 further comprising a first localized dielectric region formed in the semiconductor substrate and confined below the lower surface of one of the pair of filled striped trenches, wherein the first localized dielectric region is further confined within the first region and spaced apart from the substrate.
11. The device of claim 10 further comprising a second localized dielectric region formed in the semiconductor substrate and confined below the lower surface of another of the pair of filled striped trenches, wherein a portion of the first region laterally separates the first and second localized dielectric regions, and wherein the second localized dielectric region is further confined within the first region and spaced apart from the substrate.
12. A lateral IGFET device comprising:
a first region of a first conductivity type formed as part of a second conductivity type semiconductor substrate;
a body region of the second conductivity type formed in the semiconductor substrate adjacent the first region;
a source region of the first conductivity type formed in the body region;
a drain contact region of the first conductivity type formed in the first region;
a gate structure formed adjacent to the body region; and
a super junction structure formed in the first region, the super junction structure including:
a pair of spaced apart insulated trenches, wherein the pair of spaced apart insulated trenches has bottom surfaces that terminate within the first region;
a first localized insulating region formed confined along the bottom surface of a first insulated trench;
a second localized insulating region separate and distinct from the first localized insulating region formed confined along the bottom surface of a second insulated trench, wherein the first and second localized insulating regions are confined within the first region and separated from the semiconductor substrate by the first region;
a first striped doped region of the first conductivity type formed between the pair of spaced apart insulated trenches; and
a second striped doped region of the second conductivity type formed between the pair of spaced apart insulated trenches, wherein the first and second striped doped regions terminate in the first region without wrapping entirely around the bottom surfaces of the first and second insulated trenches.
13. The device of claim 12 further comprising a third striped doped region of the first conductivity type between the pair of spaced apart insulated trenches, wherein the third doped region terminates in the first region without wrapping entirely around the bottom surfaces.
14. The device of claim 12 further comprising a third striped doped region of the second conductivity type between the pair of spaced apart insulated trenches, wherein the third doped region terminates in the first region without wrapping entirely around the bottom surfaces.
15. The device of claim 12 , wherein the gate structure comprises a planar gate structure, the device further comprising a trench gate structure formed adjacent the body region.