IP Library Granted Patent US 7,821,095
Granted Patent B2
US 7,821,095 · App. 11/457,678 · Granted Oct 26, 2010

Method of forming a Schottky diode and structure therefor

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Quick Facts
Patent No.
US 7,821,095
App. No.
11/457,678
Granted
Oct 26, 2010
Kind
B2
Abstract

In one embodiment, a Schottky diode is formed on a doped region having a thickness less than about eighteen microns.

Claims (22)

1. A method of forming a Schottky diode comprising:

providing a semiconductor substrate having a first surface;

forming a first doped region extending into the semiconductor substrate from the first surface and having a resistivity no greater than about two ohm-cm;

forming a second doped region within the first doped region and extending less than first distance into the semiconductor substrate;

forming a Schottky barrier material contacting the first doped region;

forming a dielectric layer on the first surface and extending to overlie the second doped region and have a side substantially coplanar to an edge of the first doped region; and

forming a semi-insulating layer on the dielectric layer including forming a first semi-insulating layer on the dielectric layer and forming a second semi-insulating layer on the first semi-insulating layer.

2. The method of claim 1 wherein the Schottky diode has a reverse breakdown voltage less than about one hundred volts.

3. The method of claim 1 wherein forming the dielectric layer on the first surface includes forming the dielectric layer having a first portion of a first thickness on the first surface and extending to overlie a first portion of the second doped region and having a second portion of a second thickness overlying a second portion of the second doped region.

4. The method of claim 1 wherein forming the first doped region extending into the semiconductor substrate includes forming the first distance less than about eighteen microns.

5. The method of claim 1 wherein forming the first doped region extending into the semiconductor substrate includes forming the first doped region with a resistivity that is greater than a resistivity of the semiconductor substrate.

6. The method of claim 1 wherein forming the first and second semi-insulating layers includes forming the first semi-insulating layer having a first resistivity and the second semi-insulating layer having a second resistivity.

7. The method of claim 6 wherein forming the first and second semi-insulating layers includes forming the second resistivity greater than about 1E17 ohm-cm.

8. The method of claim 6 wherein forming the first and second semi-insulating layers includes forming the first resistivity lower than the second resistivity.

9. A method of forming a Schottky diode having a breakdown voltage less than about one hundred volts comprising:

providing a semiconductor substrate having a first surface;

forming a first doped region extending less than about eighteen microns into the semiconductor substrate from the first surface and having a resistivity no greater than about 0.2 ohm-cm;

forming a second doped region within the first doped region;

forming a Schottky barrier material contacting the first doped region;

forming a dielectric layer on the first surface and extending to overlie the second doped region and have an edge substantially coplanar to an edge of the first doped region; and

forming a semi-insulating layer on the dielectric layer including forming a first semi-insulating layer of a first resistivity disposed on the dielectric layer and forming a second semi-insulating layer of a second resistivity that is greater than the first resistivity wherein the second resistivity is no less than about 1E17 ohm-cm.

10. The method of claim 9 wherein forming the dielectric layer includes forming the dielectric layer having a first portion of a first thickness on the first surface and extending to overlie a first portion of the second doped region and having a second portion of a second thickness overlying a second portion of the second doped region.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 4, 2014
From: JPMORGAN CHASE BANK, N.A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033686/0092 →
SECURITY AGREEMENT Recorded Sep 10, 2007
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 019795/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2006
From: MORENO, ROGELIO J.; CHEN, LINGHUI
To: SEMICONDUCOT COMPONENTS INDUSTRIES, LLC
Reel/Frame 017937/0620 →