Edge seal for a semiconductor device and method therefor
View Patent ↗In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.
1. A method of forming an edge seal region of a semiconductor die comprising:
providing a substrate of a first conductivity type;
forming an active region of a first semiconductor die on a first portion of the substrate and forming an active region of a second semiconductor die on a second portion of the substrate wherein a third portion of the substrate is positioned between the first and second portions of the substrate;
forming a first dielectric layer on a surface of the substrate overlying the third portion of the substrate;
forming a second dielectric layer overlying the first dielectric layer;
forming a passivation layer overlying the second dielectric layer;
forming an opening through a portion of the passivation layer, the second dielectric layer, and the first dielectric layer and exposing a region of the surface of the substrate that is within the third portion of the substrate wherein a first edge of the second dielectric layer is exposed along a sidewall of the opening;
forming a doped region of the first conductivity type on the surface of the substrate through the opening and substantially aligned to the first edge of the second dielectric layer; and
forming a metal on a portion of the doped region and abutting the first dielectric layer and the passivation layer.
2. The method of claim 1 wherein forming the metal includes forming the metal abutting an edge of the first dielectric layer.
3. The method of claim 1 wherein forming the metal includes forming the metal as a metal spacer mechanically and electrically contacting the doped region.
4. The method of claim 1 further including forming a conductor layer on the second dielectric layer prior to forming the passivation layer wherein an edge of the conductor layer is exposed along the sidewall of the opening and electrically contacting the metal.
5. The method of claim 1 wherein forming the doped region includes implanting the doped region through the opening and using the passivation layer as a mask for the step of implanting the doped region.
6. The method of claim 1 wherein forming the doped region includes not heating the doped region to a temperature that exceeds a temperature that is required to sinter the metal and wherein the temperature is less than six hundred degrees Celsius.
7. The method of claim 1 wherein forming the doped region includes not heating the doped region to a temperature that exceeds 600 degrees Celsius.
8. The method of claim 1 wherein forming the opening includes using the passivation layer as a mask for forming the opening.
9. The method of claim 1 wherein forming the metal includes forming the metal abutting the first dielectric layer and the first edge of the second dielectric layer.
10. The method of claim 1 wherein forming the metal on the portion of the doped region includes applying a layer of metal overlying the passivation layer and through the opening onto the surface of the substrate, and anisotropically etching the layer of metal to remove portions of the layer of metal overlying the passivation layer and leaving portions of the layer of metal on the doped region and abutting the first dielectric layer.
11. The method of claim 1 wherein forming the first dielectric layer includes forming a field oxide.