IP Library Granted Patent US 7,732,925
Granted Patent B2
US 7,732,925 · App. 11/055,707 · Granted Jun 8, 2010

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,732,925
App. No.
11/055,707
Granted
Jun 8, 2010
Kind
B2
Abstract

A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.

Claims (23)

1. A semiconductor device comprising:

a monolithic silicon substrate;

a first insulation layer formed on a front surface of the substrate;

a pad electrode formed on the first insulation layer;

a supporting member bonded to the front surface so as to cover the pad electrode, the substrate having a via hole formed therein and extending from a back surface of the substrate to a surface of the pad electrode; and

a second insulation layer formed in the via hole,

wherein the via hole comprises a wide portion that is closer to the front surface than to the back surface and is wider than a narrow portion of the via hole that is closer to the back surface than to the front surface,

the first insulation layer has an opening located at the pad electrode, and the second insulation layer bends at a boundary between the substrate and the first insulation layer so as to extend into the opening to cover a side edge of the first insulation layer in the opening to prevent insulation failure in the via hole, and

one end of the wide portion of the via hole is at a plane defined by the front surface of the substrate.

2. The semiconductor device of claim 1 , further comprising a metal layer formed on a sidewall of the via hole, wherein the via hole has a hollow portion that is not filled by the metal layer.

3. The semiconductor device of claim 2 , wherein the metal layer is in contact with the surface of the pad electrode and extends along the back surface of the substrate.

4. The semiconductor device of claim 3 , further comprising a terminal disposed on the metal layer extending along the back surface of the substrate.

5. The semiconductor device of claim 2 , wherein the metal layer is in contact with the second insulation layer on the sidewall of the via hole at the wide portion of the via hole.

6. The semiconductor device of claim 3 , wherein the portion of the metal layer in the via hole and the portion of the metal layer on the back surface of the substrate are parts of a layer formed by the same process steps.

7. The semiconductor device of claim 1 , wherein the wide portion of the via hole is in contact with the first insulation layer.

8. A semiconductor device comprising:

a monolithic silicon substrate;

a first insulation layer formed on a front surface of the substrate;

a pad electrode formed on the first insulation layer, the substrate having a via hole formed therein and extending from a back surface of the substrate to a surface of the pad electrode; and

a second insulation layer formed in the via hole,

wherein the via hole comprises a wide portion that is closer to the front surface than to the back surface and is wider than a narrow portion of the via hole that is closer to the back surface than to the front surface,

the first insulation layer has an opening located at the pad electrode, and the second insulation layer bends at a boundary between the substrate and the first insulation layer so as to extend into the opening to cover a side edge of the first insulation layer in the opening to prevent insulation failure in the via hole, and

one end of the wide portion of the via hole is at a plane defined by the front surface of the substrate.

Assignments (8)
CHANGE OF NAME AND ADDRESS Recorded Jun 23, 2020
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 053010/0842 →
CHANGE OF NAME Recorded Aug 13, 2019
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 050064/0702 →
MERGER Recorded Aug 8, 2019
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 049999/0375 →
DEMERGER Recorded Aug 6, 2019
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 049969/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2015
From: NEC CORPORATION
To: SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035727/0186 →
CHANGE OF NAME Recorded Dec 5, 2011
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 027327/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2009
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022248/0521 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2005
From: OKAYAMA, YOSHIO; SUZUKI, AKIRA; KAMEYAMA, KOUJIRO; UMEMOTO, MITSUO; TAKAHASHI, KENJI; TERAO, HIROSHI; HOSHINO, MASATAKA
To: SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; FUJITSU LIMITED; NEC CORPORATION
Reel/Frame 016573/0015 →