Multiple dual bit memory integrated circuit system
View Patent ↗A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.
1. A multiple dual bit integrated circuit system comprising:
forming first address lines in a semiconductor substrate;
forming a charge-trapping layer on or over the semiconductor substrate;
forming a semiconductor layer on or over the charge-trapping layer; and
forming second address lines spaced apart in the semiconductor layer on the charge-trapping layer on and between the first address lines to form a plurality of dual bit locations.
2. The system as claimed in claim 1 wherein forming the semiconductor layer uses a silicon on dielectric forming process.
3. The system as claimed in claim 1 wherein forming the second address lines uses an implantation process.
4. The system as claimed in claim 1 further comprising:
forming a further charge-trapping layer over the semiconductor layer;
forming a further semiconductor layer over the further charge-trapping layer; and
forming further address lines in the further semiconductor layer.
5. The system as claimed in claim 4 wherein forming the further address lines forms the further address lines offset from the first address lines in the semiconductor substrate.
6. A multiple dual bit integrated circuit system comprising:
forming conductive bit lines in a first semiconductor material;
forming a charge-trapping dielectric layer over the first semiconductor material;
forming a second semiconductor material over the charge-trapping dielectric layer; and
forming conductive word lines spaced apart in the second semiconductor material on the charge-trapping dielectric layer on and between the conductive bit lines to form an array core region having a plurality of dual bit locations.
7. The system as claimed in claim 6 wherein forming the second semiconductor material uses a silicon on dielectric forming process or a polyamorphous silicon deposition process.
8. The system as claimed in claim 6 wherein forming the word lines uses an implantation process using the same dopant as the bit lines.
9. The system as claimed in claim 6 further comprising:
forming a further charge-trapping dielectric layer over the second semiconductor material;
forming a further semiconductor material over the further charge-trapping dielectric layer; and
forming further bit lines in the further semiconductor layer.
10. The system as claimed in claim 9 wherein:
forming the further bit lines forms the further bit lines offset from the bit lines in the first semiconductor material; and
further comprising:
forming contacts to the bit lines in the first semiconductor material.
11. A multiple dual bit integrated circuit system comprising:
a semiconductor substrate;
first address lines in the semiconductor substrate;
a charge-trapping layer over the semiconductor substrate;
a semiconductor layer on or over the charge-trapping layer; and
second address lines spaced apart in the semiconductor layer on the charge-trapping layer on and between the first address lines to form a plurality of dual bit locations.
12. The system as claimed in claim 11 wherein the semiconductor layer is single crystalline silicon.
13. The system as claimed in claim 11 wherein the second address lines are formed of dopants in silicon.
14. The system as claimed in claim 11 further comprising:
a further charge-trapping layer over the semiconductor layer;
a further semiconductor layer over the further charge-trapping layer; and
further address lines in the further semiconductor layer.
15. The system as claimed in claim 14 wherein the further address lines forms the further address lines offset from the first address lines in the semiconductor substrate.
16. A multiple dual bit integrated circuit system comprising:
conductive bit lines in a first semiconductor material;
a charge-trapping dielectric layer over the first semiconductor material;
a second semiconductor material over the charge-trapping dielectric layer; and
conductive word lines spaced apart in the second semiconductor material on the charge-trapping dielectric layer on and between the conductive bit lines to form an array core region having a plurality of dual bit locations.
17. The system as claimed in claim 16 wherein the second semiconductor material uses single crystalline silicon or polyamorphous silicon.
18. The system as claimed in claim 16 wherein the word lines and bit lines have the same dopant.
19. The system as claimed in claim 16 further comprising:
a further charge-trapping dielectric layer over the second semiconductor material;
a further semiconductor material over the further charge-trapping dielectric layer; and
further bit lines in the further semiconductor layer.
20. The system as claimed in claim 19 wherein:
the further bit lines are offset from the bit lines in the first semiconductor material; and
further comprising:
contacts to the bit lines in the first semiconductor material.