Non-volatile memory device with increased reliability
View Patent ↗A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
1. A method of manufacturing a semiconductor device, comprising:
forming a plurality of memory cells, each of the memory cells comprising a charge storage element and a control gate;
forming a first dielectric over the control gate;
forming at least one metal layer over the first dielectric; and
depositing a second dielectric over the at least one metal layer at a temperature of less than about 400° C.,
wherein the forming at least one metal layer comprises forming a first copper layer and a second copper layer, the method further comprising:
forming an interlayer dielectric between the first and second copper layers at a temperature of less than about 400° C.
2. The method of claim 1 , wherein the second dielectric comprises at least one of an oxide, a silicon rich oxide, a silicon oxynitride, a silicon oxycarbide, a silicon carbonitride or a hydrogenated silicon oxycarbide.
3. The method of claim 1 , wherein the depositing the second dielectric comprises:
depositing the second dielectric at a temperature of less than 350° C.
4. A method of forming a memory device, comprising:
forming a first dielectric layer formed over a substrate;
forming a charge storage element formed over the first dielectric layer;
forming a second dielectric layer formed over the charge storage element;
forming a control gate over the second dielectric layer;
forming a third dielectric layer formed over the control gate;
depositing at least one copper layer over the third dielectric layer; and
depositing a fourth dielectric layer at a temperature ranging from about 25° C. to about 385° C. over the at least one copper layer, the fourth dielectric layer comprising a cap layer for the memory device.
5. The method of claim 4 , wherein the depositing a fourth dielectric layer comprises depositing at least one of an oxide, a silicon rich oxide, a silicon oxynitride, a silicon oxycarbide, a silicon carbonitride or a hydrogenated silicon oxycarbide.
6. The method of claim 4 , wherein the depositing a fourth dielectric layer comprises depositing the fourth dielectric layer at a temperature of about 350° C.
7. The method of claim 4 , wherein the depositing at least one copper layer comprises:
depositing a first copper layer and a second copper layer, the first copper layer being deposited over the third dielectric layer, the method further comprising:
forming an interlayer dielectric between the first and second copper layers.
8. The method of claim 7 , wherein the forming an interlayer dielectric comprises:
depositing the interlayer dielectric at a temperature of less than 400° C.
9. The method of claim 4 , wherein the cap layer is formed at or near an upper surface of the memory device.
10. The method of claim 4 , wherein the forming a charge storage element comprises forming a nitride charge storage element.
11. A method of forming a non-volatile memory device, comprising:
forming a plurality of memory cells;
forming a first interlayer dielectric over the plurality of memory cells;
depositing a first metal layer over the first interlayer dielectric;
forming a second interlayer dielectric over the first metal layer at a temperature of less than about 400° C.;
depositing a second metal layer over the second interlayer dielectric; and
forming a dielectric layer over the second metal layer at a temperature of less than about 400° C.
12. The method of claim 11 , wherein the forming a first metal layer comprises depositing a first copper layer.
13. The method of claim 12 , wherein the forming a second metal layer comprises depositing a second copper layer.
14. The method of claim 11 , wherein the forming a dielectric layer comprises forming a cap layer at or near an upper surface of the non-volatile memory device.
15. The method of claim 11 , wherein the forming a dielectric layer comprises forming a cap layer for the non-volatile memory device to a thickness ranging from about 3,000 Å to about 20,000 Å.
16. The method of claim 11 , wherein the forming a dielectric layer comprises forming at least one of a silicon oxynitride, a silicon oxycarbide, a silicon carbonitride or a hydrogenated silicon oxycarbide.
17. The method of claim 11 , wherein the forming a dielectric layer comprises depositing the dielectric layer at a temperature of less than 350° C.
18. The method of claim 11 , wherein the forming a plurality of memory cells comprises:
forming a charge storage element configured to store two bits of information for each memory cell.