IP Library Granted Patent US 7,456,083
Granted Patent B2
US 7,456,083 · App. 11/069,061 · Granted Nov 25, 2008

Semiconductor device and manufacturing method of the same

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Quick Facts
Patent No.
US 7,456,083
App. No.
11/069,061
Granted
Nov 25, 2008
Kind
B2
Abstract

The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.

Claims (26)

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a resin layer disposed on a front surface of the semiconductor wafer, a first electrode pad and a second electrode pad that are formed on the front surface, and a supporting member attached to the front surface by the resin layer, the semiconductor wafer comprising a plurality of semiconductor die regions;

forming on a back surface of the semiconductor wafer a first alignment mark and a second alignment mark so that the first alignment mark is disposed in a first semiconductor die region and the second alignment mark is disposed in a second semiconductor die region that is next to the first semiconductor die region;

detecting positions of the first and second alignment marks;

calculating a middle position between the positions of the first and second alignment marks;

aligning a blade with the calculated middle position on a side of the semiconductor wafer corresponding to the back surface; and

cutting using the aligned blade at the calculated middle position the resin layer disposed on the front surface between the first and second electrode pads and along a predetermined direction.

2. The method of claim 1 , wherein the predetermined direction is a direction normal to a direction connecting the first and second alignment marks.

3. The method of claim 1 , wherein the detecting is performed using a recognition camera.

4. The method of claim 1 , further comprising etching the semiconductor wafer from the back surface to expose the first and second electrode pads.

5. The method of claim 1 , wherein the first and second alignment marks are formed of a material used in a manufacturing process of the semiconductor device.

6. The method of claim 1 , wherein the first and second alignment marks are dents formed by etching.

7. The method of claim 1 , further comprising another detecting of the positions of the first and second alignment marks, another calculating of the middle position, placing a blade at the calculated middle position, and cutting the supporting member at the calculated middle position along the predetermined direction so as to form individual semiconductor dies.

8. The method of claim 7 , wherein the first and second alignment marks are formed of a material used in a manufacturing process of the semiconductor device.

9. The method of claim 7 , wherein the first and second alignment marks are dents formed by etching.

10. The method of claim 1 , wherein the first and second alignment marks are disposed with a first dicing region interposed there between, the first alignment mark being disposed at a corner of the first semiconductor die region and the second alignment mark being disposed at a corner of the second semiconductor die region adjacent to the first semiconductor die region.

11. The method of claim 10 , further comprising forming on the back surface of the semiconductor wafer a third alignment mark and a fourth alignment mark, wherein the third and fourth alignment marks are disposed with a second dicing region interposed there between, the second dicing region crossing the first dicing region, the third alignment mark being disposed at a corner of the first semiconductor die region and the fourth alignment mark being disposed at a corner of a third semiconductor die region, the third semiconductor die region being adjacent to the first semiconductor die region.

12. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a layer disposed on a front surface of the semiconductor wafer, a first electrode pad and a second electrode pad that are formed on the front surface, and a supporting member attached to the front surface

forming on a back surface of the semiconductor wafer a first alignment mark and a second alignment mark;

detecting positions of the first and second alignment marks;

calculating a middle position between the positions of the first and second alignment marks;

aligning a blade with the calculated middle position on a side of the semiconductor wafer corresponding to the back surface; and

cutting using the aligned blade at the calculated middle position the layer disposed on the front surface between the first and second electrode pads and along a predetermined direction,

wherein the blade reaches the supporting member so as to form a groove in the supporting member.

13. The method of claim 12 , further comprising forming a protection film on the back surface of the semiconductor wafer including in the groove.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2014
From: KANTO SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033713/0296 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →