Total ionizing dose suppression transistor architecture
View Patent ↗A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.
1. A radiation-hardened transistor, comprising:
an active region surrounded by a first oxide layer;
a gate crossing the active region, defining first and second source/drain regions;
a second oxide layer covering the active region and the gate; and
a single metal region directly disposed on a top surface of the second oxide layer overlapping the boundary of the active region and completely surrounding each of the ends of the gate that extends beyond the border of the active region,
such that negative charge buildup is suppressed during exposure to ionizing radiation.
2. The radiation-hardened device of claim 1 , wherein the transistor comprises an N-channel transistor.
3. The radiation-hardened device of claim 1 , wherein the metal region is coupled to ground.
4. The radiation-hardened device of claim 1 , wherein the gate comprises a polysilicon or metal gate.
5. A radiation-hardened transistor, comprising:
an active region surrounded by a first oxide layer;
a gate crossing the active region, defining first and second source/drain regions;
a second oxide layer covering the active region and the gate; and
a single metal region directly disposed on a top surface of the second oxide layer overlapping the boundary of the active region, completely surrounding a first end of the gate extending beyond the border of the active region, and completely covering a second end of the gate extending beyond the border of the active region,
such that negative charge buildup is suppressed during exposure to ionizing radiation.
6. The radiation-hardened device of claim 5 , wherein the transistor comprises an N-channel transistor.
7. The radiation-hardened device of claim 5 , wherein the metal region is coupled to ground.
8. The radiation-hardened device of claim 5 , wherein the gate comprises a polysilicon or metal gate.