High-density memory module utilizing low-density memory components

1. A memory module having a first memory capacity, the memory module comprising:

a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another;

a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank; and

a termination bus, each pair of memory components comprising a first memory component having a first data strobe pin, a first termination signal pin in electrical communication with the termination bus, a first termination circuit, and at least one data pin, wherein the first termination circuit selectively electrically terminates the first data strobe pin and the at least one data pin of the first memory component in response to a first signal received by the first termination signal pin from the termination bus.

2. The memory module of claim 1 , wherein each pair of memory components comprises a second memory component having a second data strobe pin in electrical communication with the first data strobe pin, a second termination signal pin, a second termination circuit, and at least one data pin, wherein the second termination circuit is responsive to a voltage applied to the second termination signal pin by not terminating the second data strobe pin or the at least one data pin of the second memory component.

3. The memory module of claim 2 , further comprising at least one termination assembly having a third termination signal pin, a third termination circuit, and at least one termination pin electrically coupled to the at least one data pin of the second memory component, the third termination signal pin in electrical communication with the termination bus, wherein the third termination circuit selectively electrically terminates the at least one data pin of the second memory component through the termination pin in response to a second signal received by the third termination signal pin from the termination bus.

4. The memory module of claim 3 , wherein the first signal and the second signal are the same signal.

5. The memory module of claim 3 , wherein the termination bus comprises an on-die termination (ODT) bus, and each of the first termination circuit, second termination circuit, and third termination circuit comprises an ODT circuit.

6. The memory module of claim 3 , wherein the voltage is ground.

7. The memory module of claim 1 , wherein the memory components of each pair of memory components has a first bit width and each pair of memory components simulates a single virtual memory component having a second bit width which is twice the first bit width.

8. The memory module of claim 7 , wherein the first bit width is 4 bits, 8 bits, or 16 bits.

9. The memory module of claim 1 , wherein each of the memory components comprises ball-grid-array (BGA) packaging.

10. The memory module of claim 9 , wherein each of the memory components comprises fine-pitch BGA (FBGA) packaging.

11. The memory module of claim 1 , wherein each of the memory components comprises a synchronous dynamic random-access memory (SDRAM) integrated circuit.

12. A memory module having a first memory capacity, the memory module comprising:

a plurality of substantially identical memory components configured as a first rank and a second rank, the memory components of the first rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another, the memory components of the second rank configured in pairs, the memory components of each pair having their respective data strobe pins in electrical communication with one another; and

a logic element which receives a first set of address and control signals compatible with a second memory capacity, the second memory capacity substantially equal to one-half of the first memory capacity, wherein the logic element translates the first set of address and control signals into a second set of address and control signals compatible with the first memory capacity of the memory module, the logic element transmitting the second set of address and control signals to the first rank and the second rank, wherein each memory component has a first bit width, a first number of banks of memory locations, a first number of row address bits, and a first number of column address bits, the memory module further comprising a serial-presence-detect (SPD) device comprising data that characterizes each pair of memory components as a virtual memory component having a second bit width equal to twice the first bit width, a second number of banks of memory locations equal to the first number of banks, a second number of row address bits equal to the first number of row address bits, and a second number of column address bits equal to the first number of column address bits.

13. The memory module of claim 12 , wherein byte 3 of the SPD data comprises the first number of row address bits, byte 4 of the SPD data comprises the first number of column address bits, byte 13 of the SPD data comprises the second bit width, byte 14 of the SPD data comprises the second bit width, and byte 17 of the SPD data comprises the first number of banks.

14. The memory module of claim 13 , wherein the first bit width is 4 bits.

15. The memory module of claim 13 , wherein the first bit width is 8 bits.

16. The memory module of claim 13 , wherein the SPD device comprises an electrically-erasable programmable read-only memory (EEPROM) device.

17. The memory module of claim 12 , wherein the memory module has a 1-GB (128M×8-byte) configuration, and comprises eight pairs of memory components, each memory component having a 512-Mb (128M×4-bit) configuration, wherein the second bit width is 8 bits, the first number of row address bits is 13, and the second number of column address bits is 12.

18. The memory module of claim 12 , wherein each of the memory components comprises ball-grid-array (BGA) packaging.

19. The memory module of claim 18 , wherein each of the memory components comprises fine-pitch BGA (FBGA) packaging.

20. The memory module of claim 12 , wherein each of the memory components comprises a synchronous dynamic random-access memory (SDRAM) integrated circuit.