Use of data latches in cache operations of non-volatile memories
View Patent ↗Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.
1. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and
during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches,
wherein the first operation includes multiple phases and wherein caching said second data includes reading the second data from a second group of memory cells distinct from the first group of memory cells, the second data set being read between phases of the first operation,
wherein the first operation is a write operation having alternating program and verify phases and the first set of data is the data to be written into the first group of memory cells,
wherein said memory cells are multi-level memory cells storing N bits of data, where N is greater than one, and wherein each of said sets of data latches includes N data latches and said first data set is N bit data, and
wherein as bits of the N bits of data verify, data latches of said set of data latches are released and said cached data is stored in the released data latches.
2. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and
during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches, wherein said first operation is an erase operation and the second operation is a read.
3. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and
during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches, wherein said first operation is an erase operation and the second operation is a programming operation.
4. A method of operating a non-volatile memory device which includes an array of memory cells each storing at least N bits of data, where N is greater than one, and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
storing a first, N-bit set of data for a first group of memory cells in N data latches in each of the corresponding sets of data latches;
writing the first set of data into said first group of memory cells, wherein the writing includes alternating program and verify phases, and wherein once the group of memory cells have been programmed past one or more but less than all of the verify levels, one or more of the N data latches in each of the corresponding groups of data latches is released prior to completing said writing; and
transferring a second set of data into the released data latches prior to completing said writing.
5. The method of claim 4 , wherein said second set of data is for a second group of memory cells of the array upon which the set of read/write circuits is able to operate, wherein the second group of memory cells is different from the first group of memory cells.
6. The method of claim 4 , said transferring comprising:
reading said second set of data from said second group of memory cells into the released latches, wherein said read is performed between pulses of said writing.
7. The method of claim 4 , said transferring comprising:
transferring out said second set of data from the released latches, wherein said transferring is begun prior to completing said writing.