High reliability electrically erasable and programmable read-only memory (EEPROM)
View Patent ↗An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.
1. An Electrically Erasable and Programmable Read-Only-Memory (EEPROM) cell of a first polarity type comprising the following:
a field effect transistor of the first polarity type comprising:
a bulk terminal comprising a first well of a second polarity type opposite the first polarity type, wherein the first well is shared by a first plurality of other EEPROM cells;
a gate terminal comprising a conductive layer formed over the first well;
a first dielectric layer disposed between the gate terminal and the first well, wherein the first dielectric layer is a tunneling dielectric layer;
a source terminal of the first polarity type disposed within the first well; and
a drain terminal of the first polarity type disposed within the first well; and
a capacitor comprising:
a first terminal electrically connected to the gate terminal of the field effect transistor;
a second terminal comprising a second well of the second polarity type underneath the first terminal, the second well being shared by a second plurality of other EEPROM cells; and
a second dielectric layer disposed within the first terminal and the second terminal of the capacitor.
2. An EEPROM cell in accordance with claim 1 , wherein the first polarity type is N-type, and the second polarity type is P-type.
3. An EEPROM cell in accordance with claim 1 , wherein the first polarity type is P-type, and the second polarity type is N-type.
4. An EEPROM cell in accordance with claim 1 , wherein the EEPROM cell is disposed within an EEPROM cell array comprising a plurality of rows, wherein the first plurality of other EEPROM cells is all of the other EEPROM cells in the EEPROM cell array, and the second plurality of other EEPROM cells is all of the other EEPROM cells in the same row as the EEPROM cell.
5. An EEPROM cell in accordance with claim 1 , wherein the EEPROM cell is fabricated using exclusively CMOS technology.
6. An EEPROM cell in accordance with claim 1 , wherein the field effect transistor is fabricated using exclusively CMOS technology.
7. An EEPROM cell in accordance with claim 1 , wherein the conductive layer is formed of polysilicon having the first polarity type.
8. An EEPROM cell in accordance with claim 1 , wherein the first dielectric layer and the second dielectric layer are formed from the same process steps.
9. An EEPROM cell in accordance with claim 1 , wherein the first terminal comprises a polysilicon layer.
10. An EEPROM cell in accordance with claim 9 , wherein the polysilicon layer is of the first polarity type.
11. An EEPROM cell in accordance with claim 9 , wherein the polysilicon layer is of the second polarity type.
12. An EEPROM cell in accordance with claim 9 , wherein the polysilicon layer has a portion of the first polarity type and a portion of the second polarity type.
13. An EEPROM cell in accordance with claim 1 , further comprising:
a metal layer overlying the first terminal; and
a conductive via electrically connecting the second well to the metal layer.
14. An EEPROM cell in accordance with claim 1 , wherein the conductive layer and the first terminal are composed of polysilicon, the EEPROM cell further comprising:
a polysilicon extension electrically connecting the conductive layer to the first terminal.
15. An EEPROM cell in accordance with claim 14 , wherein the polysilicon extension is of the second polarity type at least at some of a portion of the polysilicon extension that overlies the first well.
16. An EEPROM cell in accordance with claim 1 , wherein the first well is constructed using CMOS technology.
17. An EEPROM cell in accordance with claim 1 , wherein the first well has a lower surface concentration than CMOS technology provides.
18. An EEPROM cell in accordance with claim 1 , wherein the second well is constructed using CMOS technology.
19. An EEPROM cell in accordance with claim 1 , wherein the second well has a lower surface concentration than CMOS technology provides.
20. An EEPROM cell in accordance with claim 1 , wherein the first well and the second well overlie a pocket layer of the first polarity type.
21. An EEPROM cell in accordance with claim 1 , wherein the first plurality of other EEPROM cells comprise all of the other EEPROM cells in the same EEPROM array as the EEPROM cell.
22. An EEPROM cell in accordance with claim 21 , wherein the second plurality of other EEPROM cells comprise all of the other EEPROM cells in the same word or page as the EEPROM cell.
23. An Electrically Erasable and Programmable Read-Only-Memory (EEPROM) cell of a first polarity type comprising the following:
a field effect transistor of the first polarity type comprising:
a bulk terminal comprising a first well of a second polarity type opposite the first polarity type;
a gate terminal comprising a conductive layer formed over the first well;
a first dielectric layer disposed between the gate terminal and the first well, wherein the first dielectric layer is a tunneling dielectric layer;
a source terminal of the first polarity type disposed within the first well; and
a drain terminal of the first polarity type disposed within the first well; and
a capacitor comprising:
a first terminal electrically connected to the gate terminal of the field effect transistor, wherein the first terminal comprises a polysilicon layer that has at least a portion that is of the second polarity type;
a second terminal comprising a second well of the second polarity type underneath the first terminal, the second well being shared by a plurality of other EEPROM cells; and
a second dielectric layer disposed within the first terminal and the second terminal of the capacitor.
24. An EEPROM cell in accordance with claim 23 , wherein the first polarity type is N-type, and the second polarity type is P-type.
25. An EEPROM cell in accordance with claim 23 , wherein the first polarity type is P-type, and the second polarity type is N-type.
26. An EEPROM cell in accordance with claim 23 , wherein the EEPROM cell is disposed within an EEPROM cell array comprising a plurality of rows, wherein the plurality of other EEPROM cells is all of the other EEPROM cells in the same row as the EEPROM cell.
27. An EEPROM cell in accordance with claim 23 , wherein the conductive layer is formed of polysilicon having the first polarity type.
28. An EEPROM cell in accordance with claim 23 , wherein the first dielectric layer and the second dielectric layer are formed from the same process steps.
29. An EEPROM cell in accordance with claim 23 , further comprising:
a metal layer overlying the first terminal; and
a conductive via electrically connecting the second well to the metal layer.
30. An EEPROM cell in accordance with claim 23 , wherein the conductive layer and the first terminal are composed of polysilicon, the EEPROM cell further comprising:
a polysilicon extension electrically connecting the conductive layer to the first terminal.
31. An EEPROM cell in accordance with claim 30 , wherein the polysilicon extension is of the second polarity type at least at some of a portion of the polysilicon extension that overlies the first well.
32. An EEPROM cell in accordance with claim 23 , wherein the first well and the second well overlie a pocket layer of the first polarity type.
33. An Electrically Erasable and Programmable Read-Only-Memory (EEPROM) cell of a first polarity type comprising the following:
a field effect transistor of the first polarity type comprising:
a bulk terminal comprising a first well of a second polarity type opposite the first polarity type;
a gate terminal comprising a conductive layer formed over the first well;
a first dielectric layer disposed between the gate terminal and the first well, wherein the first dielectric layer is a tunneling dielectric layer;
a source terminal of the first polarity type disposed within the first well; and
a drain terminal of the first polarity type disposed within the first well; and
a capacitor comprising:
a first terminal electrically connected to the gate terminal of the field effect transistor;
a second terminal comprising a second well of the second polarity type underneath the first terminal, the second well being shared by a plurality of other EEPROM cells, a metal layer overlying the first terminal, and a conductive via electrically connecting the second well to the metal layer; and
a second dielectric layer disposed within the first terminal and the second terminal of the capacitor.
34. An EEPROM cell in accordance with claim 33 , wherein the first polarity type is N-type, and the second polarity type is P-type.
35. An EEPROM cell in accordance with claim 33 , wherein the first polarity type is P-type, and the second polarity type is N-type.
36. An EEPROM cell in accordance with claim 33 , wherein the EEPROM cell is disposed within an EEPROM cell array comprising a plurality of rows, wherein the plurality of other EEPROM cells is all of the other EEPROM cells in the same row as the EEPROM cell.
37. An EEPROM cell in accordance with claim 33 , wherein the conductive layer is formed of polysilicon having the first polarity type.
38. An EEPROM cell in accordance with claim 33 , wherein the first dielectric layer and the second dielectric layer are formed from the same process steps.
39. An EEPROM cell in accordance with claim 33 , wherein the conductive layer and the first terminal are composed of polysilicon, the EEPROM cell further comprising:
a polysilicon extension electrically connecting the conductive layer to the first terminal.
40. An EEPROM cell in accordance with claim 39 , wherein the polysilicon extension is of the second polarity type at least at some of a portion of the polysilicon extension that overlies the first well.
41. An EEPROM cell in accordance with claim 33 , wherein the first well and the second well overlie a pocket layer of the first polarity type.