Low power sigma delta modulator
View Patent ↗A low power analog-to-digital channel includes a decimation filter coupled to a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.
1. A device comprising:
a decimation filter including an output; and
a sigma-delta modulator coupled to the output of the decimation filter;
wherein a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator.
2. The device of claim 1 , where the decimation filter is a switched capacitor decimation filter.
3. The device of claim 1 , where the sigma-delta modulator is a fourth order cascaded modulator.
4. The device of claim 1 , where the sigma-delta modulator includes one or more successive approximation converters.
5. The device of claim 1 , where a ratio of a sampling frequency for the sigma-delta modulator to a Nyquist number for an input signal to the decimation filter is eight.
6. The device of claim 5 , where the sampling frequency is approximately 256,000 Hertz.
7. The device of claim 5 , where image rejection is greater than 55 decibels.
8. The device of claim 1 , where the output of the decimation filter places a null at a sampling frequency of the sigma-delta modulators in one or more signals received by the sigma-delta modulator.
9. The device of claim 1 , where the decimation filter operates at a clock frequency that is four times higher than a sampling frequency of the sigma-delta modulator.
10. The device of claim 1 , where the sigma-delta modulator and the decimation filter are included in one or more integrated circuits.
11. A device comprising:
a means for filtering an analog input signal including an output; and
a sigma-delta modulator coupled to the output of the means for filtering the analog input signal;
wherein a clock frequency applied to the means for filtering an analog input signal is approximately an integral multiple of a sampling frequency of the sigma delta modulator.
12. The device of claim 11 , where the output from the means for filtering an analog input signal is a differential analog signal including a first signal and a second signal.
13. The device of claim 12 , where the first signal of the differential analog signal is coupled to a first sigma-delta modulator, and the second signal of the differential analog signal is coupled to a second sigma-delta modulator.
14. The device of claim 13 , where the first sigma-delta modulator and the second sigma-delta modulator are cascaded sigma-delta modulators.
15. The device of claim 11 , where the means for filtering an analog input signal includes a switched capacitor decimation filter.
16. The device of claim 11 , where the sigma delta modulator receives a filtered differential analog signal and outputs a digital signal.
17. The device of claim 11 , where the means for filtering an analog input signal and the sigma-delta modulator include one or more integrated circuits.
18. The device of claim 11 , where the sigma-delta modulator includes one or more successive approximation converters.
19. The device of claim 11 , where a sample rate for the sigma-delta modulator is approximately sixteen times a highest frequency to be converted.
20. A method comprising:
filtering an analog signal using a decimation filter to produce a filtered signal;
applying the filtered signal to an input of a sigma-delta modulator; and
producing an output from the sigma-delta modulator.
21. The method of claim 20 , including sampling the analog signal at a rate that is 16 times the frequency of a highest frequency present in the analog signal.
22. The method of claim 20 , including operating the decimation filter at a clock speed that is a integral multiple of a sampling frequency so that the filtered signal includes a null at approximately the sampling frequency of the analog signal.