Gate electrodes of semiconductor devices and methods of manufacturing the same
View Patent ↗Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to form an auxiliary pattern; depositing a polysilicon layer; dry etching the polysilicon layer to form a side wall of the polysilicon layer to adjacent the auxiliary pattern; removing the auxiliary pattern; depositing an insulating layer; chemical mechanical polishing to remove a predetermined thickness of the side wall and the insulating layer to thereby complete the gate electrode from the side wall; and removing the insulating layer.
1. A method for manufacturing a gate electrode of a semiconductor device, comprising:
sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate;
patterning the sacrificial buffer layer to form an auxiliary pattern;
depositing a polysilicon layer;
dry etching the polysilicon layer to form a side wall of the polysilicon layer to adjacent the auxiliary pattern;
removing the auxiliary pattern;
depositing an insulating layer;
chemical mechanical polishing to remove a predetermined thickness of the side wall and the insulating layer to thereby complete the gate electrode from the side wall; and
removing the insulating layer.
2. A method as defined in claim 1 , wherein a width of the gate electrode is adjusted by adjusting a thickness of the sacrificial buffer layer.
3. A method as defined in claim 1 , wherein the sacrificial buffer layer is an oxide layer.
4. A method as defined in claim 2 , wherein the sacrificial buffer layer is an oxide layer.