IP Library Granted Patent US 7,550,372
Granted Patent B2
US 7,550,372 · App. 11/162,115 · Granted Jun 23, 2009

Method of fabricating conductive lines with silicide layer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,550,372
App. No.
11/162,115
Granted
Jun 23, 2009
Kind
B2
Abstract

A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.

Claims (21)

1. A method of fabricating conductive lines, comprising:

providing a substrate having a polysilicon layer thereon;

forming a mask layer on the polysilicon layer, wherein the mask layer has an opening that exposes a portion of the polysilicon layer;

forming spacers on the sidewalls of the opening and above the polysilicon layer;

removing a portion of the polysilicon layer using the spacers and the mask layer as a mask;

forming an insulating layer over the substrate to fill the opening, wherein the insulating layer has an etching selectivity different from the mask layer;

removing the mask layer, and the spacers not being removed so as to expose a portion of the polysilicon layer not covered by the spacers; and

forming a silicide layer on the exposed portion of the polysilicon layer.

2. The method of claim 1 , wherein the step of forming a silicide layer on the upper surface of the polysilicon layer comprises:

forming a metallic layer over the substrate;

performing an annealing process so that a portion of the metallic layer reacts with silicon to form the suicide layer; and

removing the metallic layer not participated in the reaction.

3. The method of claim 2 , wherein the material constituting the metallic layer comprises a refractory metal.

4. The method of claim 3 , wherein the material constituting the metallic layer is selected from a group consisting of cobalt, nickel, tungsten and titanium.

5. The method of claim 1 , wherein the material constituting the insulating layer comprises silicon nitride and the material constituting the mask layer comprises silicon oxide.

6. The method of claim 1 , wherein the material constituting the insulating layer comprises silicon oxide and the material constituting the mask layer comprises silicon nitride.

7. The method of claim 1 , wherein the step of forming the insulating layer over the substrate to fill the opening comprises:

forming an insulating material layer over the substrate; and

removing the insulating material layer outside the opening using the mask layer as a stop layer.

8. The method of claim 7 , wherein the step of removing the insulating material layer outside the opening using the mask layer as a stop layer comprises performing a chemical/mechanical polishing operation.

9. The method of claim 1 , wherein the spacers and the mask layer are fabricated using materials having different etching selectivity.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2020
From: POWERCHIP TECHNOLOGY CORPORATION
To: NEXCHIP SEMICONDUCTOR CORPORATION
Reel/Frame 053704/0522 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2020
From: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 052337/0735 →
CHANGE OF NAME Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0536 →